DigitaltoAnalog Conversion
Digital Circuits
If a pulsewidth modulated (PWM) signal is sent to a passive integrator circuit from a circuit capable of both sourcing and sinking current (as is the case with the dualMOSFET output stage), the output will be a DC voltage (with some ripple):

Determine the relationship between the PWM signal’s duty cycle and the DC voltage output by the integrator. What does this suggest about PWM as a means of communicating information, such as analog data from a measuring device?
A type of resistor network known as an R2R ladder is often used in digitaltoanalog conversion circuits:

When all switches in the R2R ladder are in the “ground” position, the network has a very interesting property regardless of its size. Analyze the Thévenin equivalent resistance (as seen from the output terminal) of the following R2R ladder networks, then comment on the results you obtain:





When only the most significant bit (MSB) of an R2R ladder resistor network is activated (all other bits inactive, their switches connecting to ground), the output voltage will be the same, regardless of how many bits the network has:

Explain why this output voltage magnitude stands independent of the number of bits (sections) in the R2R ladder network.
Thévenin’s theorem is a powerful tool for analyzing R2R ladder networks. Take for instance this foursection network where the nexttomostsignificant “bit” is activated, while all the other “bits” are inactive (switched to ground):

If we Thévenize all sections to the left of the activated section, replacing it with a single resistance to ground, we see the network becomes far simpler:

Explain how we may apply Thévenin’s theorem once again to the shaded section of this next circuit (simplified from the previous circuit shown above) to simplify it even more, obtaining a final result for V_{out}:

This digitaltoanalog converter (DAC) circuit takes a fourbit binary input (input terminals A through D) and converts it to an analog voltage (V_{out}). Predict how the operation of this circuit will be affected as a result of the following faults. Consider each fault independently (i.e. one at a time, no multiple faults):

 •
 Bilateral switch U_{1} fails open:
 •
 Zener diode fails shorted:
 •
 Solder bridge (short) past resistor R_{1}:
 •
 Resistor R_{6} fails open:
The following circuit generates an analog output voltage proportional to the value of the binary input, using pulsewidth modulation (PWM) as an interim format. An eightbit binary counter (CTR) continually counts in the üp” direction, while an 8bit magnitude comparator (CMP) checks when the 8bit binary input value matches the counter’s output value. The AND gate and inverter simply prevent the SR latch from being ßet” and “reset” simultaneously (when both A and B are maximum, both at a hex value of $FF), which would cause the output to be ïnvalid” when S and R were both active, and unpredictable when both S and R inputs returned to their inactive states:

Explain how this circuit works, using timing diagrams if necessary to help show the PWM signal at [Q] for different input values.
This is a digitallyset motor speed controller circuit, using PWM to modulate power to the motor. Predict how the operation of this circuit will be affected as a result of the following faults. Consider each fault independently (i.e. one at a time, no multiple faults):

 •
 DAC output fails low (output = 0 volts DC):
 •
 DAC output fails high (output = +V):
 •
 IGBT Q_{1} fails open (collector to emitter):
 •
 Solder bridge (short) between MSB input on U_{1} and ground:
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