Industry Article

RISC-V: Opening a New Era of Innovation for Embedded Design

June 27, 2018 by Ted Marena, Microsemi

This article explores the benefits behind RISC-V's open-source hardware model, discussing it's longevity, portability, and reliability.

This article explores the benefits behind RISC-V's open-source hardware model, discussing it's longevity, portability, and reliability.

The momentum behind RISC-V for embedded applications is undeniable. Today, the RISC-V Foundation has over 100 companies behind the free and open RISC-V instruction set architecture (ISA), and its membership is growing rapidly as more tools, software, hardware, and operating system vendors jump on board. With its expanding ecosystem, RISC-V gives both software and hardware designers a convincing alternative to incumbent embedded processors, sparking a new era in processor innovation in embedded designs as adoption grows.


Ted Marena presenting for the RISC-V foundation

Figure 1. The RISC-V Foundation's Marketing Chair, Ted Marena, presents on the benefits of RISC-V.


Reasons behind RISC-V unlocking a new era boil down to three key factors: longevity, portability, and reliability. All three reasons are tied to what makes RISC-V especially compelling. Unlike the already established processor architectures, which often add instructions with each generation, designers can rely on a fixed ISA with RISC-V, ensuring the longevity of their software investments. This longevity is particularly beneficial for embedded applications where functional safety, certification, and long product life cycles are important. 

A Frozen ISA

To enable the broad use of RISC-V and allow the market to dictate processor architectures, the UC Berkeley engineering team behind RISC-V froze the ISA shortly before they introduced the technology at the 25th Hot Chips Symposium in 2014. With the establishment of the non-profit RISC-V Foundation in 2015, members are tasked with directing the future development of HW/SW specifications and the ecosystem, as well as driving the adoption of the ISA. With the base ISA set in stone and optional extensions being made available, designers can implement processors tailored to their specific workloads, rather than having to work around a standard, off-the-shelf processor design that leaves little if any room for customization.

Numerous RTOS and full operating systems now support RISC-V. RISC-V is particularly attractive for embedded applications because of the growing use of the Linux OS. This enables designers to rapidly adopt the ISA as a new open standard architecture for direct native hardware implementations. However, even if Linux isn’t being used, the frozen architecture, longevity, portability, and reliability that the ISA lends itself to are key factors to consider.

RISC-V Extensions

A frozen ISA means software can be developed once and run indefinitely on any RISC-V device, which supports the extensions (if any) being used. Extensions are the only method by which new instructions can be added. Currently, there are five extensions, which have also been frozen. These extensions include:

  • M for integer multiply and divide.
  • A for atomic Instructions
  • F for single precision floating point
  • D for double precision floating point
  • C for compressed instructions

RISC-V Processor Benefits

This level of predictability and simplicity has many benefits for processor designs and software development. Let’s look at each one by one.



The RISC-V ISA offers a stable, clean-slate design platform with clear and secure separation between User and Privileged modes because the ISA is fixed and contains less than 50 instructions. If all of the multiple standard extensions are implemented, the total number is still less than 200. Instead of introducing new versions of the ISA, additions to the standard instruction set are made through extensions, facilitating additional stability in future designs. Fewer instructions mean simpler architectures can be created, leading to cost-effectiveness and power-efficiency in processor implementation. For software developers, this translates to preserved investments. Write software once and run it forever on any RISC-V core. This is often critical for products with a long product life that must be supported for decades, as well as for applications that must adhere to stringent certification requirements where software cannot be modified. 



RISC-V makes it much easier for designs to ramp up to high volume. For example, a design can start shipping in an FPGA running a soft RISC-V core (Figure 1). Since the software will be completely portable across any devices that have a RISC-V core, designers have what is essentially a “royalty-free” processor sub-system RTL code ready to be implemented in hardware. Designers can modify, adapt, and migrate their design to the best platform for their product. If the selected FPGA needs to be replaced with the next generation device, there is no need to rewrite the software code. The existing source RTL simply needs to be retargeted to the other FPGA. Additionally, if volumes reach high enough levels, the same RTL source can be retargeted to an ASIC without the need to pay any royalty fees. This scenario is not possible with an ARM or x86 type processor.


RISC V IP Core portablility chart

Figure 2. The RISC-V IP core chart.


Reliability and Safety

RISC-V’s flexibility enables unique solutions, particularly for embedded designs requiring functional safety. For example, in systems with multiple, functionally equivalent cores autonomously designed for the ultimate in redundancy. One such core could be the Microsemi Mi-V RV32IM, and the other core could be a functionally equivalent, yet completely different, in-house design. RISC-V also allows complete flexibility over the microarchitecture; so one core could provide single event upset (SEU) protective measures for data and instruction cache memory. Many other safety prevention techniques can be used because RISC-V allows access to the RTL. 

While the well-established variations of Intel x86 and ARM processor architectures are unlikely to go away anytime soon, the RISC-V processor ecosystem is poised for rapid growth in the embedded market given the freedom designers have to customize. The design of the processor architecture is inherently flexible so that an implementation can have some operations accelerated in hardware, or, for example, optimized specifically for low power. Designers also have the flexibility to attach any bus interface they desire, instead of being tied only to the buses that established processor vendors offer. Because of the fixed nature of the ISA, any variation in the RISC-V microarchitecture is acceptable. 

RISC-V Resources

To learn more about RISC-V for your next design, there are several places to get started.

For background information about RISC-V and its members, visit the RISC-V Foundation website. If you want to splash right in and begin C coding for a RISC-V core, head over to Microsemi’s Github site and check out the IGLOO2 Creative Development Board RISC-V Projects. Microsemi was the first FPGA vendor to offer an open architecture RISC-V IP core and a comprehensive software IDE solution. Designers can deploy the RISC-V IP core in multiple flash-based FPGAs, including PolarFire FPGAs, IGLOO2, and RTG4 devices. The Mi-V Creative board (Figure 2) contains an IGLOO2 FPGA preprogrammed with a RISC-V core that runs “hello world” out of the box. 

For software code development, the Eclipse-based Soft Console integrated development environment (IDE) hosted on a Linux or Windows platform provides complete development support, including a C or C++ compiler and debugger capability. The Microsemi RISC-V IP core, Libero SoC development software, and the Soft Console IDE can all be downloaded free of charge from the Microsemi Github site.


M2GL025 Creative Board with preprogrammed RISC-V Core

Figure 3. M2GL025 Creative Board with preprogrammed RISC-V Core


With its frozen ISA, simplicity, portability, and reliability, RISC-V gives designers an entirely new processor paradigm from which to reach beyond the constraints of the established processor status quo and push the boundaries of innovation.   

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