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Category: ARM Processors Reference Designs

66AK2G02 DSP + ARM Processor Audio Processing Reference Design

The TIDEP0069 TI Reference Design is a reference platform based on the 66AK2G02 DSP + ARM processor  System-On-Chip (SoC) and companion AIC3106 Audio codec and enables a quick path to audio processing algorithm design and demonstration. This audio solution design includes real time application software using the Processor SDK TI RTOS software that demonstrates audio processing block on the DSP to…
System Block Diagrams
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66AK2G02 DSP + ARM Processor Power Solution Reference Design

The TIDEP0067 TI Reference Design is  based on the 66AK2G02 multicore System-on-Chip (SoC) processor and companion TPS659118 power management integrated circuit (PMIC) which includes power supplies and power sequencing for the 66AK2G02 processor in a single device. This power solution design also includes the first stage buck converters to support a 12 V input and the DDR termination regulator…
System Block Diagrams
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DDR ECC Reference Design to Improve Memory Reliability in 66AK2G02-based Systems

The TIDEP0070 reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications: based on the 66AK2G02 Multicore DSP + ARM processor System-on-Chip (SoC).  It enables developers to implement a high reliability based solution rapidly by discussing system interfaces: board hardware: software:…
System Block Diagrams
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Flexible Interface (PRU-ICSS) Reference Design for Simultaneous: Coherent DAQ Using Multiple ADCs

This reference design showcases an interface implementation for connecting multiple high voltage bipolar input: 8-channel: mux-input SAR ADCs (6) with the Sitara Arm processors for expanding the number of input channels using Programmable Real-time Unit (PRU-ICSS). ADCs are configured for simultaneous sampling of the same channels across all ADCs. The design highlights the capability of PRU-ICSS…
System Block Diagrams
The following system block diagrams are available from Texas Instruments:

Generating AVS SmartReflex Core Voltage for K2E Using TPS544C25 and PMBus Reference Design

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
System Block Diagrams
The following system block diagrams are available from Texas Instruments:

Optimized Radar System Reference Design Using a DSP+ARM SoC

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters: who need faster time to market with increased performance and significant reduction in cost: power: and size: this reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End (DFE) processing. Connecting to the ADC14X250 and DAC38J84…
System Block Diagrams
The following system block diagrams are available from Texas Instruments:

PCI Express PCB Design Considerations Reference Design for the 66AK2G02 General Purpose EVM ‘GP EVM’

PCI-Express provides for low pin-count: high reliability: and high-speed with data transfer at rates of up to 5.0 Gbps per lane: per direction: and an PCIe module is included on the TI 66AK2G02 DSP + ARM Processor system on chip (SoC).  This PCIe PCB design considerations reference design  helps developers optimize the printed circuit board (PCB) design by providing best-practice PCB for the…
System Block Diagrams
The following system block diagrams are available from Texas Instruments:

Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor: who need faster time to market with increased performance and significant reduction in cost: power: and size. This reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End Processing (DFE). Connecting…
System Block Diagrams
The following system block diagrams are available from Texas Instruments: