Tom Wolf Tom Wolf is a Senior Product Application Engineer for Logic Devices at Nexperia.  His design and application experience extends to a wide array of systems including server/workstation design, optoelectronics, battery and energy systems and embedded controllers.

Webinar Replay - How the Small-Footprint GX 8-Pin Logic Device Reduces Manufacturing Costs

In partnership with christine@eetech.com - eetechchristine

Don’t miss this webinar!

Designing with the Industry’s Smallest Logic Devices with the Biggest Lead Pitch for Mobile, Portable, and IoT Applications

Understanding minimum pitch issues when designing for minimum footprint products has become the most important factor for design engineers today. This webinar will address solutions for the continual trend in electronic systems towards smaller and smaller footprints, lower power consumption, and lower system costs. 

Our experts will walk you through a complete range of 5-, 6- and 8-pin logic devices and how they can help you save space, power, and product assembly cost for your next design.

Expanding on the 5- and 6-pin GX package family, the GX 8-pin makes nearly every major logic function available in this new ultra-small format, allowing design and production engineers to more agilely respond to market requirements. Measuring just 0.8mm x 1.2mm and only 0.35 mm in height, the GX 8-pin (SOT1233) package is especially suitable for mobile, portable, and IoT applications and not only saves space but also reduces PCB assembly costs and improves ruggedness.

Attendees will learn:

  • • The minimum pin pitch issues while designing for minimum footprint applications 
  • • How to avoid using a step-down solder mask, reducing manufacturing costs and the risks of solder bridges
  • • The complete range of 5-, 6-, and 8-pin GX devices and how to take advantage of the unique design configuration and pad placement

Who should attend?

  • • Engineering managers
  • • Design engineers
  • • Design managers
  • • System architects....and anyone else interested in reducing design cycle times and PCB assembly cost

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