Industry White Paper
Accelerate Early Design Exploration and Verification for Faster Time to Market
March 23, 2021 by Siemens Digital Industries Software
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White Paper Overview
Early chip-level physical verification faces many challenges. The Calibre™ Recon tool enables design teams to perform analysis and physical verification of full-chip design layouts during the very early stages of the design cycle, while the different components are still immature. With Calibre Recon, designers can quickly and easily find and resolve integration issues using the foundry/IDM Calibre sign-off design kit, while reducing total DRC runtime, accelerating design closure, and ensuring high-quality designs.
In this white paper you will learn about:
- The challenges of chip-level verification
- How to improve dirty block/chip-level verification
- Automatic check selection
- The Calibre nmDRC Recon gray box feature
- The Calibre nmDRC Recon DRC Analyze function
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