Accelerate Time-to-Market with Calibre nmLVS Recon™ Technology: A New Paradigm for Circuit Verification

Whitepaper Overview 

When it comes to design, one thing is clear — tapeouts are getting harder and are taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS-Recon tool enables design teams to rapidly examine unfinished designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time-to-market.

Calibre nmLVS-Recon™ provides a similar benefit to design teams, system-on-chip (SoC) engineers, and circuit verification teams by delivering an intelligent process that enables users to leverage innovative options for data partitioning, data re-use, task distribution, and errors management that can help them achieve faster layout vs. schematic (LVS) iterations on dirty designs.

Calibre nmLVS-Recon™ Features 

• Finds and fixes shorts during the early stages of design implementation
• Provides selective verification for faster runtimes, enabling significantly more
iterations
• Integrates debugging supports quick error visualization for faster and more
efficient debugging
• Reduces overall tapeout schedules by minimizing the number of signoff
iterations required

In this whitepaper from Mentor, a Siemens Business, learn more about Calibre nmLVS-Recon™ and how it can help accelerate time-to-market.