Accelerate Time to Market with Calibre nmLVS Recon Technology: A New Paradigm for Circuit Verification

White Paper Overview

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year. These delays are caused by multiple factors, including design for manufacturing (DFM) optimization, performance metrics fulfillment, timing closure, and the sheer length of time needed to run the signoff verification cycle.

While the verification process is not the only contributor to delays in the design cycle, it is a significant contributor to overall signoff process duration. This impact can be attributed to increases in design complexity, design sizes, number of devices, number of polygons, new types of devices, and more complex measurements and parameter calculations.

This white paper from Siemens Digital Industries Software provides a detailed look at how the Calibre nMLVS Recon solution enables faster identification, better debugging, and fixing of selective circuit issues by leveraging similar capabilities for partitioning, categorization, prioritization, data re-use, and task distribution.