Industry White Paper

IROC Technologies Tapes Out Aerospace SoC with Aprisa Place-and-Route

Case Study Overview

For this project, ESA asked IROC to assess the suitability of Ultra Deep Submicron (UDSM) technology nodes below 22 nm for space applications. ESA requires high reliability in their chips and systems when faced with threats from the operating environment. For aerospace applications, one of the most important threats is single events (soft errors) caused by radiation at high altitudes and in cosmic space.

IROC’s challenge was to build an IC to act as the test vehicle for accurately measuring the reliability of an array of devices (such as standard cells, memories and IP) to measure the effect of single events or soft errors on those devices due to radiation at various altitudes. In addition to containing the structures to be measured, the chip needed to include the measuring circuitry itself, which should not be sensitive to the types of soft errors being evaluated. And, they had a tape-out deadline of three months.

IROC contacted the Aprisa team and they began working together to determine what software and support was needed for the project. The Aprisa software is a detail-route-centric physical design platform for the modern SoC. Designers get excellent quality-of-results and fast runtimes. Aprisa helps designers avoid iterations, improves power/performance/area tradeoffs, and reduces time-to-closure by pulling detail-route visibility earlier in the flow.

In this case study, learn how the Aprisa software was able to implement a powerful and flexible RTL-GDSII design flow that was easy to use, fast, technology ready, and with excellent correlation with sign-off to reduce iterations.

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