Industry White Paper

Spartan UltraScale+ FPGA Delivers High I/O & Low Power in a Small Package

March 20, 2024 by Rob Bauer, AMD

Introducing the Spartan UltraScale+ FPGA Family—Delivering High I/O & Low Power in a Small Package

Editor’s Note: This content is contributed by Rob Bauer, Sr. Product Marketing Manager

Hardware designers building embedded applications have long made difficult tradeoffs, balancing cost, I/O count, and logic density requirements with the need to achieve fast time-to-market. We’re excited to announce a solution that renders those tradeoffs obsolete: the new AMD Spartan™ UltraScale+™ FPGA low-cost family, which offers high I/O-to-logic-cell ratios, low power, and state-of-the-art security features in a small form factor.

The AMD Spartan UltraScale+ FPGA family delivers a competitive balance of price, power, features, and size, complementing the rest of our cost-optimized portfolio, which includes five previous Spartan families along with the Artix™ 7 and Artix UltraScale+ families.

With Spartan UltraScale+ FPGAs, designers can achieve rapid time-to-market for cost-sensitive, I/O-intensive applications while working with AMD, a partner offering 40 years of experience in FPGAs and access to easy-to-use, all-in-one tools, such as the AMD Vivado™ Design Suite.

Delivering High I/O, Low Power, and State-of-the-Art Security Features for a Wide Range of Applications

AMD Spartan UltraScale+ FPGAs are equipped with the highest I/O-to-logic-cell ratio in our cost-optimized portfolio for any-to-any connectivity.1 They provide comprehensive I/O capabilities from 1.2V to 3.3V and support single-ended and differential standards for maximum interface versatility.

The devices offer advanced connectivity with up to eight GTH transceivers running at 16.3 Gb/s. They support comprehensive MIPI D-PHY interfaces up to 3.2 Gb/s, as well as multiple PCIe® Gen4 interfaces.

AMD Spartan UltraScale+ FPGAs capitalize on the proven 16 nm architecture, offering significant power savings—up to a 30% reduction in total power compared to the previous 28 nm series on lower densities2—while delivering up to 1.9X fabric performance.3 For applications requiring high-performance interfaces like LPDDR4x/LPDDR5 memory or PCIe® Gen4, the larger Spartan UltraScale+ FPGAs also include hardened IP, improving overall power efficiency up to 60%4 and enhancing overall system performance. The hardened IP also frees up programmable logic resources, making these devices ideally suited for power- and space-constrained environments.

In addition to power savings, high I/O, and broad connectivity, the AMD Spartan UltraScale+ FPGA family includes state-of-the-art security features to protect your IP, prevent tampering, and maximize uptime. These include NIST post quantum cryptography (PQC) ready, physical unclonable function (PUF) for unique device identification, primary and secondary public key (PPK/SPK) for authentication, true number random generator (TRNG) for encryption, and more.

With packaging options as small as 10 mm x 10 mm, AMD Spartan UltraScale+ devices offer flexible deployment for industrial networking, robotics, embedded vision, healthcare, AV and broadcast, automotive, and other I/O-intensive applications.

Accelerate Time-to-Market with Proven Design Tools

Like all modern devices in the AMD cost-optimized portfolio, the AMD Spartan UltraScale+ family is supported by the Vivado Design Suite, which is a single, easy-to-use tool, while other FPGA vendors’ products often necessitate the use of multiple tools. Combined with a rich IP catalog and machine-learning-based power optimization capabilities, the tool allows designers to work more productively and speed time-to-market.

Design Once with a Trusted Supplier

I’m proud to share this exciting news about our AMD Spartan UltraScale+ family, the latest addition to a robust portfolio of FPGAs spanning 40 years. When you partner with AMD, you get the confidence of knowing your designs will have longevity. We endeavor to support our devices for 15 years or more, beyond industry standards. Additionally, you get access to a range of devices both within our cost-optimized portfolio and in the mid- and high-end for design scalability.

With the new AMD Spartan UltraScale+ FPGA family, you can maximize capability while reducing cost and power consumption. More importantly, you get the support of a partner for the long haul, with devices suited to all of your diverse applications and needs.

Discover how this exciting new offering can help you solve your next design challenge.


  1. Based on AMD internal analysis in December 2023, comparing the total I/O-to-logic-cell ratios in the AMD product datasheets for Spartan™ UltraScale+™ FPGAs to previous generations of AMD cost-optimized FPGAs.
  2. Projection is based on AMD Labs internal analysis in January 2024, using a total power calculation (static plus dynamic power), based on the difference in logic cell count of an AMD Artix UltraScale+ AU7P FPGA, to estimate the power of a 16 nm AMD Spartan™ UltraScale+™ SU35P FPGA versus a 28 nm AMD Artix 7 7A35T FPGA using Xilinx Power Estimator (XPE) tool version 2023.1.2. Actual total power will vary when final products are released in market, based on configuration, usage, and other factors.
  3. Projection is based on AMD Labs internal analysis in January 2024, using nine different designs on two devices, Artix UltraScale+ AU10P FPGA as a scale to Spartan UltraScale+ FPGA versus a 28 nm Artix 7 7A100T FPGA, that were run at different clocks for Fmax calculation. The constraints were set so that the device ran at its max performance. Performance results may vary based on configuration, usage, and other factors.
  4. Projection is based on AMD internal analysis in January 2024, using a total power calculation (static plus dynamic power) based on the logic scale count of the AU7P to estimate the total power of Spartan UltraScale+ SU200P versus Artix 7 7A200T, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Actual total power may vary when final products are released in market, based on configuration, usage, and other factors.



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