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Introducing Calibre nmLVS-Recon
OMRP (Openpattern Modular Routing Platform) is the first product-oriented project of the OpenPattern company. The target is to create a new open…
An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths. An table of taps for selected widths is used to…
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Features - direct traceback option. - self test automation - support any popular convolution code. - throughput and area of decoder are scalable. -…
A FPGA development board based on EP2C35F672, with SDRAM and flash .
Summary The Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which…
Griva Basic 1.2v - FPGA development kit ,, , Highlights , , , , , , , , , * Xilinx Spartan3E XS3S250E or XC3S500E -PQG208 , , , , , , , , , , , , ,…
The IIE-PCI Development Platform board is a low cost PCI device card with a programmable logic chip (Altera ACEX), dynamic ram, and expansion…
Project to create generic emulator/debugger/analyzer with on-the-fly reprogrammable firmware on Artec Dongle II board (containing Altera Cyclone…
If you liked our work is want to help contribute to the future progress of others who have seen help us by donating. ###…
An FPGA Board with the largest Artix 7 XC7A200T FPGA, USB 2.0 controller, Flash memory, 100 GPIO's and on-board voltage regulators. Features…
Discrete Multi Tone (DMT) is the modulation scheme used for Asymmetric Digital Subscriber Line (ADSL) systems and one of the modulation schemes…
A HyperTransport Tunnel controller written in SystemC. HyperTransport (HT) is a high-performance chip-to-chip interconnect architecture. A tunnel…
This project consists of the translation of the USB 1.1 Function IP Core Verilog code and dependencies, maintained by Rudolf Usselmann, into a…
This is a simple UART implementation with intention to valid ASIC learning and use it on simple applications. The environment was rebuild with…
Features - Latency insensitive design - Should be portable to most bus architectures/platforms - Easily amenable to multi-clock domain extension -…
This IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list. Sorting is acheived using a…
A SystemC/Verilog synthesizable MD5 hash core. This work is given by Universidad Rey Juan Carlos (Spain) For more info about our projects visit…
SystemC DES is a implementation of the DES algorithm in SystemC focusing on low area applications. Implements the encoder and decoder in the same…
Cascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded…
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