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Category: All IP Cores (12)

Generic Galois LFSR Generator in MyHDL

An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths. An table of taps for selected widths is used to…

License : LGPL
Language : Other

Reconfigurable Hardware Platform

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Other

EP2C35 FPGA Development Board

A FPGA development board based on EP2C35F672, with SDRAM and flash .

License : LGPL
Language : Other

Prototype Griva Basic Board

Griva Basic 1.2v - FPGA development kit ,, , Highlights , , , , , , , , , * Xilinx Spartan3E XS3S250E or XC3S500E -PQG208 , , , , , , , , , , , , ,…

License : LGPL
Language : Other

8bit LPC SPI ROM Emulator Artec Dongle II Board

Project to create generic emulator/debugger/analyzer with on-the-fly reprogrammable firmware on Artec Dongle II board (containing Altera Cyclone…

License : LGPL
Language : Other

SystemC/Verilog MD5 Hash Core Standard

A SystemC/Verilog synthesizable MD5 hash core. This work is given by Universidad Rey Juan Carlos (Spain) For more info about our projects visit…

License : LGPL
Language : Other

Cascaded Integrator-comb (CIC) Digital Filter Core

Cascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded…

License : LGPL
Language : Other

Advanced Debug Interface for Multi-device JTAG Chains

The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a…

License : LGPL
Language : Other

myBlaze - a synthesizable clone of the MicroBlaze Soft Processor

myBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in myHDL ( http://www.myhdl.org ). It started as a translation of MB-Lite…

License : LGPL
Language : Other

NoCmodel - Python Module for Network-on-Chip Modeling

NoCmodel is a Python module for Network-on-Chip modeling, with add-ons for simulation (functional or RTL) and code generation (initially VHDL).…

License : LGPL
Language : Other

4-bit System

This project shows a 4-bit open system done with Quartus II v12

License : LGPL
Language : Other

Uart2BusTestBench

Uart2BusTestBench is implemented using Universal Verification Methodology to perform the functional verification to the RTL design released by Moti…

License : LGPL
Language : Other