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Category: All IP Cores (26)

Huffman Decoder for Streaming Application

Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the…

License : Others
Language : VHDL

3-input Ternary Adders for Altera and Xilinx

This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx…

License : Others
Language : VHDL

Multi-function Universal CORDIC IP Core

kvcordic is a collection of files comprising an implementation of a universal CORDIC algorithm (rotation/vectoring direction,…

License : Others
Language : VHDL

Fade Light L3 Ethernet PHY Protocol

This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an…

License : Others
Language : VHDL

High-speed FT2232H USB Avalon Core

The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style…

License : Others
Language : VHDL

Simple UART Contorller for FPGAs

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART…

License : Others
Language : VHDL

Universal Configurable Wishbone AXI with Xilinx IP Wrapper

WishboneAXI This project is a universal, configurable Wishbone AXI bridge together with Xilinx IP wrapper, which makes it suitable for Block Design…

License : Others
Wishbone Version : B.3
Language : VHDL

IOTA PoW Computation Pearl-Driver for FPGAs

Overview IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. This is a…

License : Others
Language : VHDL

Configurable VIIRF - Versatile IIR Filter for Any Transfer Function

This project comprises the VHDL description and configuration script of a configurable IIR filter. The VIIRF can implement any transfer function…

License : Others
Language : VHDL

2nd order Sigma-Delta DAC

Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA.…

License : Others
Language : VHDL

VHDL 6532 RIOT (RAM-I/O-TIMER)

VHDL implementation of the 6532 RIOT (RAM-I/O-TIMER) Like the original chip from Mostek/Rockwell, this component is 6500/6800 bus compatible. The…

License : Others
Language : VHDL

Artificial Intelligence System Using FGPA/ASIC

The Artificial Intelligence System is a neuromorphic FPGA/ASIC project undertaken by a number of volunteers with the scope of simulating real-time…

License : Others
Language : VHDL

Dynamic Vectorial Generator

Vectorial generator: -Interface: bit or bus -Configuration: dynamic -Applications: waveform generator, serial or parallel communication Examples:…

License : Others
Language : VHDL

GECKO4 SoC Co-design Environment

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : VHDL

LXP32 - FPGA-friendly Lightweight Open Source 32-bit CPU Core

LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward…

License : Others
Wishbone Version : B.3
Language : VHDL

Plasma with FPU - Based on MIPS I implementation

This project is based on an implementation of MIPS I specified core by Steve Rhoads: plasma Interface entity plasma is generic( core_idx : natural…

License : Others
Language : VHDL

Plasma CPU - Small Synthesizable 32-bit RISC Microprocessor

The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART,…

License : Others
Language : VHDL

TinyVLIW8 8-bit Soft-core Processor in VHDL

The tinyVLIW8 is a 8-bit soft-core processor for deeply embedded control task. The design is fully implemented in VHDL and tested on the Altera DK1…

License : Others
Language : VHDL

GECKO3 SoC General Purpose Co-design Environment

The GECKO system is a general purpose hardware/software co-design environment for real-time information processing and/or system-on-chip (SoC)…

License : Others
Language : VHDL

Software Defined Radio CCSDS RX/TX SoC

Software Defined Radio RX/TX. Consultative Committee for Space Data System (CCSDS) specifications compliant. This is part of a larger project…

License : Others
Language : VHDL