Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: BCD Adder

Filters

Category: All IP Cores (432)

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

Introduction The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform…

License : LGPL
Language : Verilog

Digital Video Broadcasting (DVB-S2) LDPC Decoder

Introduction: From my thesis: Low-Density Parity Check (LDPC) coding is a form of error coding introduced by Gallager that can achieve performance…

License : LGPL
Language : Verilog

Verilog Fixed Point Math Library

Synopsis Hey, this project has been downloaded many, *many* times it would seem. I'm glad you've found it useful. I would be interested in…

License : LGPL
Language : Verilog

2D FHT - Two Dimensional Fast Hartley Transform

RTL Verilog code to perform Two Dimensional Fast Hartley Transform (2D-FHT) for 8x8 points. Presented algorithm is FHT with decimation in frequency…

License : LGPL
Language : Verilog

Configurable Cordic Core in Verilog

A 100% behavioral implementation of a cordic core. The core is highly configurable through `defines. A testbench is included. See the included…

Language : Verilog

Configurable CRC Core in Verilog

n/a

License : LGPL
Language : Verilog

CORDIC Arctangent for IQ Signals

Streaming atan function based on CORDIC algorithm. [angle, modulus] = cordic([I, Q]) angle = atan(Q/I) modulus = sqrt(I^2+Q^2) angle in range…

License : LGPL
Language : Verilog

CRCAHB

Arithmetic core originally created by: Cesar, Julio Fernandes, Felipe //// CRCAHB CORE BLOCK This file is part of the APB to I2C project…

License : LGPL
Language : Verilog

Double Precision Floating Point Unit IEEE-754 Compliant

Features - The unit is designed to be synchronous to one global clock. All registers are updated on the rising edge of the clock. - All registers…

License : LGPL
Language : Verilog

FT816 Floating Point Accelerator

07/06/2019 - Updated the square root core to allow restarting the calculation any time load is active. 06/14/2019 - Updates have been made to…

License : LGPL
Language : Verilog

Elliptic Curve Group Core

The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements…

License : LGPL
Language : Verilog

Fixed Point Arithmetic Modules Verilog

This project was started in order to create fixed point (Q format) arithmetic modules in verilog. What was created was a parameterized (specify…

License : LGPL
Language : Verilog

Gaussian Noise Generator for FPGAs

The Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low…

License : LGPL
Language : Verilog

FPGA-based Median Filter Architecture

This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture…

License : LGPL
Language : Verilog

MESI Coherency InterSection Controller

The MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It…

License : LGPL
Language : Verilog

Fast Base-2 Log Function in Single-Cycle

A fast (single-cycle) base-2 log function, based on the description at http://www.cantares.on.caextras.html Need an electronic design solution?…

License : LGPL
Language : Verilog

Simple Mod 3 Calculator

A quick & simple mod 3 calculator(only just combinational logic). the input 8-bit data is divided by 3. and the output is only 0, 1, or 2. I…

License : LGPL
Language : Verilog

Number Sorting Device O (N)

// number sorting device, sequential, 2*N clocks for N // linear buffer implementation // sequential, stable, can be partly readed, decreasing…

License : LGPL
Language : Verilog

Parameterizable Integer Square Root by Digit-by-digit Method

SystemVerilog: y = sqrt(x); x, y - unsigned integers. Parameterizable streaming integer square root function by the digit-by-digit method.

License : LGPL
Language : Verilog

Verilog Parameterizable Adder Tree

Parameterizable Verilog module that calculate sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array…

License : LGPL
Language : Verilog