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Category: All IP Cores (21)

Tiny Tate Bilinear Pairing Core

Tiny Tate Bilinear Pairing core is for calculating Tate bilinear pairing. In fact it is a special type of Tate bilinear pairing called reduced…

License : Others
Language : Verilog

Fast AES-128 Encryption Only Cores

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License : Others
Language : Verilog

SATA Controller in Verilog

Sata stack written in Verilog , , Staus: , , , ,Nysa SATA Github, , , Code Organization: , , sata_stack.v (Top File that applications interface…

License : Others
Language : Verilog

Bidirectional TCP Socket for FPGA

TCP Socket TCP Socket is a TCP/IP stack implementation. The core acts as a server, allowing a remote client to establish a bidirectional TCP socket…

License : Others
Language : Verilog

vSPI - Verilog Implementation of SPI Slave

=== What's "vSPI"? === vSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably…

License : Others
Language : Verilog

Three Cores AES Encryption Algorithm

AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS…

License : Others
Language : Verilog

AES with Galois Counter Mode in FPGA

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License : Others
Language : Verilog

NIST SHA-3 Algorithm (Keccak)

SHA-3, originally known as Keccak [1], is a cryptographic hash function selected as the winner of the NIST hash function competition [2]. Because…

License : Others
Language : Verilog

Common Design Environment (CDE) Library

Common Design Environment (CDE) is a library of modules that usually require replacement with specific hard macros when the design is retargeted to…

License : Others
Language : Verilog

MyGPU Library for FPU Units

MyGPU is a library of large-scale components like FPU units, a processor and auxillary units which can be used to build SoCs, processors, etc. We…

License : Others
Language : Verilog

FPGA Based Srdy-Drdy Library on Common Data-Transfer Protocol

The srdy-drdy library provides a group of components all built around a common data-transfer protocol. This protocol is used in datapath…

License : Others
Language : Verilog

GroundHog 2009 Repository - Benchmark Suite For Mobile Apps

GroundHog 2009 is a benchmark suite for reconfigurable architectures in the mobile domain. The benchmark suite can be downloaded from…

License : Others
Language : Verilog

ELM Embedded Processor

n/a

License : Others
Language : Verilog

FWRISC - Featherweight RISC-V RV32I Implementation

FWRISC is a Featherweight RISC-V RV32I implementation. All instructions and registers are supported. Source is hosted on GitHub:…

License : Others
Language : Verilog

HIVE - a 32-bit General Purpose Soft Processor Core

Quick link to the design document v08.06: http://www.mediafire.com/view/vp3hb8phe3t5yh4Hive_Design_2015-09-03.pdf Quick link to everything…

License : Others
Language : Verilog

RISC16f84 for Small, Easy to Use Microcontroller in Verilog

The risc16f84 project is intended to provide a small, easy to use microcontroller in Verilog. The original code was VHDL, but I have done a…

License : Others
Language : Verilog

Small Stack Based Computer Compiler with a 9-bit Opcode, 8-bit Data Core

Summary SSBCC.9x8 is a free Small Stack-Based Computer Compiler with a 9-bit opcode, 8-bit data core. It creates vendor-independent, high-speed,…

License : Others
Language : Verilog

High Performance Image Warping/Texture Mapping Core

Texture mapping unit tailored for Milkdrop acceleration. This core was designed for Milkymist, a highly integrated opensource VJing platform. See…

License : Others
Language : Verilog

ARINC 429 Transmitter And Receiver

The aim of this project is to provide a set of ARINC-429-compatible TX and RX synthesizable interfaces. The transmitting interface serializes a…

License : Others
Language : Verilog

Documented Verilog UART

Open Source Documented Verilog UART Purpose This module was created as a result of my own need for a UART (serial line I/O) component and…

License : Others
Language : Verilog