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Category: All IP Cores (34)

Heap Sorter Algorithm for FPGA

This project implements a sorter able to sort a continuous stream of data, consisting of records labeled with "sort keys". Sorter sorts…

License : BSD
Language : VHDL

Simple Parametrized FFT Engine

This project implements a simple parametrized FFT engine. The user may define length of FFT (fftlen equal to a power of 2), and may also define the…

License : BSD
Language : VHDL

Synthesized Sine And Cosine Table in VHDL

Sine and cosine table that can be synthesized. Pure VHDL, no other tools or silicon vendor macros. Pipeline delay can be selected from…

License : BSD
Language : VHDL

IGOR - Microprogrammed LISP Machine

Norwegian University of Science and Technology This project came to be because of the course "TDT4295 - Computer Design, Project", due to…

License : BSD
Language : VHDL

1Gbit Ethernet UDP IP Stack

Implements UDP, IPv4, ARP protocols Zero latency between UDP and MAC layer (combinatorial transfer during user data phase) Allows full control of…

License : BSD
Language : VHDL

Open-source FPGA Communication Framework

FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a…

License : BSD
Language : Verilog & VHDL

IICMB Core - I2C Multiple Bus Controller

The IICMB core provides low-speed, two-wire, bidirectional serial bus interfaces compliant to industry standard I2C protocol. The key feature of…

License : BSD
Language : VHDL

HDB3/HDB2/B3ZS Encoder Decoder

This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T…

License : BSD
Language : VHDL

SDHC Self Configuring Core

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License : BSD
Language : VHDL

UART to Bus IP Core for Fast and Easy Test FPGA

Have you ever needed a fast and easy way to test your new FPGA board? You know you have all the interfaces but it will take time to finish the…

License : BSD
Language : Verilog & VHDL

WRIMM Based Wishbone Interconnect System

Wrimm provides Wishbone interconnect functionality, multi-master arbitration, multi-slave partial address deccoding and bus multiplexing. Wrimm…

License : BSD
Language : VHDL

AES Encryption All Keylength

Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely,…

License : BSD
Language : VHDL

Avalon AES ECB Core (128, 192, 256 Bit)

General Description I know there are plenty of AES (Rijndael) implementations around. I created my own anyway because I was unhappy with either the…

License : BSD
Language : VHDL

Mini Advanced Encryption Standard - Mini AES

Mini AES Advanced Encryption Standard (AES) implementation with small area/resources utilization. Features - Encryption and Decryption unit in…

License : BSD
Language : VHDL

Nugroho Free Crypto Cores

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License : BSD
Language : VHDL

Nugroho Free Hash Cores

Nugroho Free Hash Cores (NFHC) currently support SHA-1, SHA-256, SHA-512 from FIPS-180 standard.

License : BSD
Language : VHDL

Secure Hash Standard SHA256 Algorithm

SHA256 running at 199.788MHz on Xilinx's 28nm Kintex 7 speed grade 3 device. Processing speed: 1.598 Gbits per second. Also added an optimised…

License : BSD
Language : VHDL

Tiny Encryption Algorithm (TEA)

1 and 64 stage implementations of the Tiny Encryption Algorithm (TEA).

License : BSD
Language : VHDL

Product Code Iterative Decoder

Product Code Iterative Decoder An iterative decoder for Product Code, this decoder works for two dimensional product code. Status - Synthesized…

License : BSD
Language : VHDL

Simple Implementation of FM Receiver

Simple FM Receiver Simple implementation of FM Receiver to demodulate square wave signal modulated in FM. This design uses PLL to demodulate FM…

License : BSD
Language : VHDL