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Category: All IP Cores (36)

Suslik Scalar Risc CPU

Scalar risc cpu of my own architecture which features dynamic branch predictor (1-bit), single cycle load from l1 data cache, 4-way set-associative…

License : BSD
Language : Verilog

Open-source FPGA Communication Framework

FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a…

License : BSD
Language : Verilog & VHDL

Wishbone I2C Controller Core for Communications

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the…

License : BSD
Wishbone Version : B.3
Language : Verilog

ISO7816 3 Master on FPGA

This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine. This is a work in progress.…

License : BSD
Language : Verilog

RTF Simple UART Core with BAUD Generator

This is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit. + baudX8/X16 mode selects in…

License : BSD
Language : Verilog

Scan Based Serial Communication Block

This is a scan based serial communication block designed to safely and easily move data onto and off of a chip with a minimal number of pins.…

License : BSD
Language : Verilog

UART to Bus IP Core for Fast and Easy Test FPGA

Have you ever needed a fast and easy way to test your new FPGA board? You know you have all the interfaces but it will take time to finish the…

License : BSD
Language : Verilog & VHDL

UDP/IP Core for PC-FPGA Communication

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : BSD
Language : Verilog

GOST 28147-89 Core Implementation on Xilinx

This is a implementation of the GOST 28147-89 - a Soviet and Russian government standard symmetric key block cipher. GOST 28147-89 has a 64-bit…

License : BSD
Language : Verilog

GOST 28147-89 Block Cipher

The GOST block cipher, defined in standard GOST 28147-89, is a Soviet and Russian government standard symmetric key block cipher. Developed in the…

License : BSD
Language : Verilog

IMA ADPCM Audio Compressor

The IMA ADPCM audio compression algorithm belongs to the Adaptive Differential Pulse Code Modulation type algorithms. The algorithm is based on a…

License : BSD
Language : Verilog

Simple backtracking 9x9 Sudoku Solver in Verilog

Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C…

License : BSD
Language : Verilog

Computer Operating Properly : Watchdog Timer Module

The Computer Operating Properly Module, COP, is a watchdog timer module that triggers a system reset if it is not regularly serviced by writing two…

License : BSD
Language : Verilog

16-Bit Programmable Interval Timer Module

The Programmable Interval Timer Module, PIT, is a simple timer to generate a periodic signal for a microcontroller system. This signal may be used…

License : BSD
Language : Verilog

Scalable Synchronous Round-robin Arbiter

A scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speeds with up to hundreds of request lines, and it…

License : BSD
Language : Verilog

ao486 - x86 Compatible Verilog Core

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX. The core was modeled and tested based on the Bochs software x86…

License : BSD
Language : Verilog

aoR3000 - MIPS R3000A Compatible Core

The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74…

License : BSD
Language : Verilog

Classic 5-Stage Pipeline MIPS 32-bit Processor

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a 1024 depth branch prediction buffer, a 2KB direct-mapped…

License : BSD
Language : Verilog

openMSP430 - Synthesizable 16-bit Microcontroller Core

Introduction The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430…

License : BSD
Language : Verilog

Software Aided Wishbone Extension For Xilinx (R) PicoBlaze (TM)

This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or…

License : BSD
Language : Verilog & VHDL