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Introducing Calibre nmLVS-Recon
Forasmuch as many have taken in hand to set forth a UART core, ... It seemed good to me also, having had perfect (a good) understanding of all…
Built out of necessity, this core is designed to provide a conversion from a wishbone bus to an AXI bus. Primarily, the core is designed to connect…
This is a Quad-SPI Flash controller. It currently works for me on the 4MB Spansion flash found within a Basys-3 development board. The controller…
If a FPGA or CPLD needs to be coupled to a microcontroller often a fast interface is needed. Many controllers do not provide an external…
AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…
The original goal of the ZIP CPU was to be a very simple CPU. You might think of it as a poor man's alternative to the OpenRISC architecture.…
This CMOD-S6 SoC grew out of the desire to demonstrate that a useful ZipCPU soft core implementation could be made in a very small space. In…
This project attempts to take two separate projects, the OpenCores ZipCPU and Xess.com's XuLA2-LX25, and merge them together into a single…
The purpose of the OpenArty project is to implement a ZipCPU on an Arty platform, together with open source drivers for all of the Arty…
Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory…
This is a wishbone accessible scope or logic analyzer. Connect this scope internally to your favorite 32-bits of information from internal to your…
The SDSPI controller offered here exports an high level SD card interface to the rest of an FPGA core via a wishbone bus. Interaction at the lower…
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