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Category: All IP Cores (9)

Standalone Population Counter Generator

C code for generating a stand-alone population counter with user-defined size (number of input bits) and latency (number of clock cycles) in VHDL.

License : LGPL
Language : C/C++

Reed Solomon Decoder for OFDM Wireless Systems

This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems. Source code provided in C++ (trunk/cpp-source) and…

License : LGPL
Language : C/C++

USB NAND Flash Reader

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : C/C++

LFSR Counter Generator Up to 63 bit, Cross-Platform Compatible

LFSR Counter Generator is a command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The…

License : LGPL
Language : C/C++

Parallel CRC Generator Command-line Application

CRC Generator is a command-line application that generates Verilog or VHDL code for a parallel CRC of any data width between 1 and 1024 and…

License : LGPL
Language : C/C++

8-bit Pipelined Processor

n/a

License : LGPL
Language : C/C++

EziDebug - Easy-to-use Versatile Logic Simulation Tool

EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in…

License : LGPL
Language : C/C++

JTAG Chains with JAM STAPL Player

Converts Raspberry Pi into a JTAG programmer (STAPL protocol). Supports two JTAG chains through 26-pin RPi GPIO P1 connector. The TCK rate is…

License : LGPL
Language : C/C++

Constrained Random Test Generator

Constrained random testing enables us to cover many more system behaviors through random input variations, random fault injections, and automatic…

License : LGPL
Language : C/C++