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Category: All IP Cores (54)

OMRP Prototype Board V2

OMRP (Openpattern Modular Routing Platform) is the first product-oriented project of the OpenPattern company. The target is to create a new open…

License : Others
Language : Other

Huffman Decoder for Streaming Application

Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the…

License : Others
Language : VHDL

Tiny Tate Bilinear Pairing Core

Tiny Tate Bilinear Pairing core is for calculating Tate bilinear pairing. In fact it is a special type of Tate bilinear pairing called reduced…

License : Others
Language : Verilog

3-input Ternary Adders for Altera and Xilinx

This IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx…

License : Others
Language : VHDL

Multi-function Universal CORDIC IP Core

kvcordic is a collection of files comprising an implementation of a universal CORDIC algorithm (rotation/vectoring direction,…

License : Others
Language : VHDL

Butterfly Light FPGA Development Board

Summary The Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which…

License : Others
Language : Other

SpaceWire SystemC

If you liked our work is want to help contribute to the future progress of others who have seen help us by donating. ###…

License : Others
Language : Other

Fast AES-128 Encryption Only Cores

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License : Others
Language : Verilog

Fade Light L3 Ethernet PHY Protocol

This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an…

License : Others
Language : VHDL

High-speed FT2232H USB Avalon Core

The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style…

License : Others
Language : VHDL

SATA Controller in Verilog

Sata stack written in Verilog , , Staus: , , , ,Nysa SATA Github, , , Code Organization: , , sata_stack.v (Top File that applications interface…

License : Others
Language : Verilog

Simple UART Contorller for FPGAs

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART…

License : Others
Language : VHDL

Bidirectional TCP Socket for FPGA

TCP Socket TCP Socket is a TCP/IP stack implementation. The core acts as a server, allowing a remote client to establish a bidirectional TCP socket…

License : Others
Language : Verilog

UART 8 SystemC Implementation

This is a simple UART implementation with intention to valid ASIC learning and use it on simple applications. The environment was rebuild with…

License : Others
Language : Other

vSPI - Verilog Implementation of SPI Slave

=== What's "vSPI"? === vSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably…

License : Others
Language : Verilog

Three Cores AES Encryption Algorithm

AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS…

License : Others
Language : Verilog

Universal Configurable Wishbone AXI with Xilinx IP Wrapper

WishboneAXI This project is a universal, configurable Wishbone AXI bridge together with Xilinx IP wrapper, which makes it suitable for Block Design…

License : Others
Wishbone Version : B.3
Language : VHDL

AES with Galois Counter Mode in FPGA

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License : Others
Language : Verilog

IOTA PoW Computation Pearl-Driver for FPGAs

Overview IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. This is a…

License : Others
Language : VHDL

NIST SHA-3 Algorithm (Keccak)

SHA-3, originally known as Keccak [1], is a cryptographic hash function selected as the winner of the NIST hash function competition [2]. Because…

License : Others
Language : Verilog