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Category: All IP Cores (6)

Wishbone I2C Controller Core for Communications

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the…

License : BSD
Wishbone Version : B.3
Language : Verilog

Universal Configurable Wishbone AXI with Xilinx IP Wrapper

WishboneAXI This project is a universal, configurable Wishbone AXI bridge together with Xilinx IP wrapper, which makes it suitable for Block Design…

License : Others
Wishbone Version : B.3
Language : VHDL

VHDL Whisbone Test Bench

For the development of IP cores a test bench is needed. The given project provides a test bench written in VHDL which controls the stimulus,the…

License : LGPL
Wishbone Version : B.3
Language : VHDL

LXP32 - FPGA-friendly Lightweight Open Source 32-bit CPU Core

LXP32 is a lightweight, open source and FPGA-friendly 32-bit CPU IP core. It uses a simple, original instruction set designed for straightforward…

License : Others
Wishbone Version : B.3
Language : VHDL

ZAP - Pipelined ARM Compatible core with cache and MMU

ZAP : ARM compatible core with cache and MMU (ARMv4T ISA compatible) Author : Revanth Kamaraj (revanth91kamaraj@gmail.com) License : GPL v2…

License : GPL
Wishbone Version : B.3
Language : Verilog

Martins SoC Instancing, Simulation Toolchain Builder

The MaSoCist is an acronym for 'Martins SoC Instancing, Simulation Toolchain'. It is a VHDL collection and toolchain based on various open…

License : Others
Wishbone Version : B.3
Language : VHDL