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Category: All IP Cores (12)

Another Wishbone Controlled UART

Forasmuch as many have taken in hand to set forth a UART core, ... It seemed good to me also, having had perfect (a good) understanding of all…

License : GPL
Wishbone Version : B.4
Language : Verilog

Pipelined Wishbone Bus to AXI Converter

Built out of necessity, this core is designed to provide a conversion from a wishbone bus to an AXI bus. Primarily, the core is designed to connect…

License : GPL
Wishbone Version : B.4
Language : Verilog

Quad SPI Flash Controller

This is a Quad-SPI Flash controller. It currently works for me on the 4MB Spansion flash found within a Basys-3 development board. The controller…

License : GPL
Wishbone Version : B.4
Language : Verilog

SPI Slave Wishbone Master Controller

If a FPGA or CPLD needs to be coupled to a microcontroller often a fast interface is needed. Many controllers do not provide an external…

License : LGPL
Wishbone Version : B.4
Language : VHDL

Avalon to Wishbone Bridge

AVALON/WISHBONE Bridge This is an Avalon to WishBone Bridge. Avalon is a bus standard mainly used in Altera(Now Intel) Tools. Wishbone as every one…

License : LGPL
Wishbone Version : B.4
Language : Verilog

ZIP 32-bit RISC CPU with GCC Support

The original goal of the ZIP CPU was to be a very simple CPU. You might think of it as a poor man's alternative to the OpenRISC architecture.…

License : GPL
Wishbone Version : B.4
Language : Verilog

CMOD S6 SoC for ZipCPU Soft Core Implementation

This CMOD-S6 SoC grew out of the desire to demonstrate that a useful ZipCPU soft core implementation could be made in a very small space. In…

License : GPL
Wishbone Version : B.4
Language : Verilog

XuLA2-LX25 SoC System on a Chip Implementation Controller

This project attempts to take two separate projects, the OpenCores ZipCPU and Xess.com's XuLA2-LX25, and merge them together into a single…

License : GPL
Wishbone Version : B.4
Language : Verilog

OpenArty - Implementing ZipCPU on an Arty platform

The purpose of the OpenArty project is to implement a ZipCPU on an Arty platform, together with open source drivers for all of the Arty…

License : GPL
Wishbone Version : B.4
Language : Verilog

Wupper: PCIe DMA Engine for Xilinx Virtex-7 FPGA Gen3 Integrated Block

Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory…

License : LGPL
Wishbone Version : B.4
Language : VHDL

Wishbone Accessible Scope | Logic Analyzer

This is a wishbone accessible scope or logic analyzer. Connect this scope internally to your favorite 32-bits of information from internal to your…

License : GPL
Wishbone Version : B.4
Language : Verilog

SPI Based SD Card Controller

The SDSPI controller offered here exports an high level SD card interface to the rest of an FPGA core via a wishbone bus. Interaction at the lower…

License : GPL
Wishbone Version : B.4
Language : Verilog