The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements…
This project was started in order to create fixed point (Q format) arithmetic modules in verilog. What was created was a parameterized (specify…
VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…
VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…
This Floating Point units were developed as part of the HAVOC project. The Design schematics and related files can be browsed at the FPU…
The Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low…
This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture…
This is a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic…
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IEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4…
The MESI InterSection Controller (ISC) is a coherence system controller. It supports the MESI coherence protocol for a cache data consistency. It…
This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…
This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed…
An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths. An table of taps for selected widths is used to…
This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…
This is a collection of synthesizeable hardware dividers. Different types of dividers are available. All dividers are fully pipelined and provide a…
Hierarchical Carry Save Algorithm (HCSA) is a modification of well known adder algorithm. Comes as VHDL IP core, shows good timing and small area…
Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the…
This project implements a sorter able to sort a continuous stream of data, consisting of records labeled with "sort keys". Sorter sorts…
Before You read This is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed…
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