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Category: Arithmetic Core IP Cores (4)

Generic Galois LFSR Generator in MyHDL

An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths. An table of taps for selected widths is used to…

License : LGPL
Language : Other

Reconfigurable Hardware Platform

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License : LGPL
Language : Other

Viterbi HDL Code Generator

Features - direct traceback option. - self test automation - support any popular convolution code. - throughput and area of decoder are scalable. -…

License : GPL
Language : Other

4-bit System

This project shows a 4-bit open system done with Quartus II v12

License : LGPL
Language : Other