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Category: Arithmetic Core IP Cores (45)

32-bit Pipelined 5x4Gbps CRC Generator

A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input…

License : GPL
Language : VHDL

Parallel Two Dimensional DCT in VHDL

NEW: 12 bit input MDCT version created by Emrah Yuce has been added to project downloads. Parallel synthesizable implementation of 2D DCT in VHDL.…

Language : VHDL

Configurable Parallel Scrambler Descrambler

This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…

License : LGPL
Language : VHDL

CORDIC Algorithm Core for Iterations

The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions…

License : GPL
Language : VHDL

openFPU64 - Open Source Double Precision FPU

Free and open source double precision Floating Point Unit (FPU). The openFPU64 currently features: - double precision - Addition/Subtraction -…

License : GPL
Language : VHDL

Fixed-Point Pipelined Quadratic Polynomial

Quadratic_func is a fully pipelined quadratic polynomial that computes the relation y = ax^2 + bx + c. On each rising-edge of the clock (when en is…

License : GPL
Language : VHDL

Efficient Floating Point Logarithm Unit for FPGAs

VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…

License : LGPL
Language : VHDL

32-bit Fixed Point Square Root (Recursive Algorithm)

VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…

License : LGPL
Language : VHDL

Floating Point Adder and Multiplier

This Floating Point units were developed as part of the HAVOC project. The Design schematics and related files can be browsed at the FPU…

Language : VHDL

32-bit Floating Point Unit (FPU)

This is a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic…

Language : VHDL

Hardware Load Balancer for Multi-Stage Software Router

n/a

License : LGPL
Language : VHDL

IEEE-754 Compliant FPU Double VHDL

IEEE-754 compliant double-precision floating point unit. 4 operations (addition, subtraction, multiplication, division) are supported, as are the 4…

Language : VHDL

Generic Galois LFSR in VHDL

This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…

License : LGPL
Language : VHDL

LZRW1 Lossless Data Compressor Core

This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed…

License : GPL
Language : VHDL

Gregory-Newton Extrapolation Algorithm (GN Extrapolator)

This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…

License : LGPL
Language : VHDL

Huffman Decoder for Streaming Application

Huffman code is used in the most streaming applications. I have written a Huffman decoder for jpeg pictures. For audio or other data streams the…

License : Others
Language : VHDL

Heap Sorter Algorithm for FPGA

This project implements a sorter able to sort a continuous stream of data, consisting of records labeled with "sort keys". Sorter sorts…

License : BSD
Language : VHDL

LCD162B Behavior Model in VHDL

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

LFSR Core - Random Number Generator

The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…

License : LGPL
Language : VHDL

Maximum/Minimum Binary Tree Finder

the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…

License : LGPL
Language : VHDL