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Category: Arithmetic Core IP Cores (5)

Heap Sorter Algorithm for FPGA

This project implements a sorter able to sort a continuous stream of data, consisting of records labeled with "sort keys". Sorter sorts…

License : BSD
Language : VHDL

Simple Parametrized FFT Engine

This project implements a simple parametrized FFT engine. The user may define length of FFT (fftlen equal to a power of 2), and may also define the…

License : BSD
Language : VHDL

Synthesized Sine And Cosine Table in VHDL

Sine and cosine table that can be synthesized. Pure VHDL, no other tools or silicon vendor macros. Pipeline delay can be selected from…

License : BSD
Language : VHDL

Suslik Scalar Risc CPU

Scalar risc cpu of my own architecture which features dynamic branch predictor (1-bit), single cycle load from l1 data cache, 4-way set-associative…

License : BSD
Language : Verilog

Cellular Automata PRNG

A cellular automata (CA) is a discrete model that consists of a grid (1D, 2D, 3D ) with objects called cells. Each cell can be in one of a given…

License : BSD
Language : Verilog