Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: BCD Adder

Filters

Category: Arithmetic Core IP Cores (34)

32-bit Pipelined 5x4Gbps CRC Generator

A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input…

License : GPL
Language : VHDL

Configurable Parallel Scrambler Descrambler

This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…

License : LGPL
Language : VHDL

CORDIC Algorithm Core for Iterations

The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions…

License : GPL
Language : VHDL

openFPU64 - Open Source Double Precision FPU

Free and open source double precision Floating Point Unit (FPU). The openFPU64 currently features: - double precision - Addition/Subtraction -…

License : GPL
Language : VHDL

Fixed-Point Pipelined Quadratic Polynomial

Quadratic_func is a fully pipelined quadratic polynomial that computes the relation y = ax^2 + bx + c. On each rising-edge of the clock (when en is…

License : GPL
Language : VHDL

Efficient Floating Point Logarithm Unit for FPGAs

VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…

License : LGPL
Language : VHDL

32-bit Fixed Point Square Root (Recursive Algorithm)

VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…

License : LGPL
Language : VHDL

Hardware Load Balancer for Multi-Stage Software Router

n/a

License : LGPL
Language : VHDL

Generic Galois LFSR in VHDL

This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…

License : LGPL
Language : VHDL

LZRW1 Lossless Data Compressor Core

This IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed…

License : GPL
Language : VHDL

Gregory-Newton Extrapolation Algorithm (GN Extrapolator)

This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…

License : LGPL
Language : VHDL

LCD162B Behavior Model in VHDL

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

LFSR Core - Random Number Generator

The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…

License : LGPL
Language : VHDL

Maximum/Minimum Binary Tree Finder

the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…

License : LGPL
Language : VHDL

MODBUS Implementation in VHDL

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

QFP32 (QuadFixedPoint32) Arithmetic Unit

QFP32 Arithmetic Core implements a full customizable arithmetic core using the QFP32 format. Available arithmetic operations are easily configured…

License : LGPL
Language : VHDL

Ray Tracing Rendering Engine

Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.…

License : LGPL
Language : VHDL

Pipeline MIPS Processor in VHDL

VHDL Implementation of a basic Pipeline MIPS processor. It has a translator of MIPS assembler code and implement the division algorithm restoring.

License : GPL
Language : VHDL

FPGA-Based PID Controller

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

Single 14 Segment Display Driver with Limited ASCII Decoder

The module expects ASCII character code (in 8-bit binary) and displays the coresponding character on single digit 14-segment monocolor LED display.…

License : LGPL
Language : VHDL