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Category: Arithmetic Core IP Cores (27)

Configurable Parallel Scrambler Descrambler

This is a behavioral module for parallel scrambler/descrambler. There are RTL scrambler modules available, the purpose of this project is to built…

License : LGPL
Language : VHDL

Efficient Floating Point Logarithm Unit for FPGAs

VHDL implementation of a fast space- and resource-efficient logarithm approximation unit for FPGAs. The unit is an implementation of the ICSILog…

License : LGPL
Language : VHDL

32-bit Fixed Point Square Root (Recursive Algorithm)

VHDL project for a Square Root Unit (SRU) for 32-bit fixed point data. The unit implements the Goldschmidt recursion algorithm. It is pipelined…

License : LGPL
Language : VHDL

Hardware Load Balancer for Multi-Stage Software Router

n/a

License : LGPL
Language : VHDL

Generic Galois LFSR in VHDL

This project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation &…

License : LGPL
Language : VHDL

Gregory-Newton Extrapolation Algorithm (GN Extrapolator)

This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows simulate and synthesize the Gregory-Newton extrapolation…

License : LGPL
Language : VHDL

LCD162B Behavior Model in VHDL

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License : LGPL
Language : VHDL

LFSR Core - Random Number Generator

The lfsr core is a random number generator based on linear feedback shift register(LFSR).The sequence generated has the maximum length possible.The…

License : LGPL
Language : VHDL

Maximum/Minimum Binary Tree Finder

the aim of this design to build combinatorial digital circuit to find in fast parallel the maximum or the minimum of set of given set data where…

License : LGPL
Language : VHDL

MODBUS Implementation in VHDL

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License : LGPL
Language : VHDL

QFP32 (QuadFixedPoint32) Arithmetic Unit

QFP32 Arithmetic Core implements a full customizable arithmetic core using the QFP32 format. Available arithmetic operations are easily configured…

License : LGPL
Language : VHDL

Ray Tracing Rendering Engine

Ray Tracing : A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.…

License : LGPL
Language : VHDL

FPGA-Based PID Controller

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License : LGPL
Language : VHDL

Single 14 Segment Display Driver with Limited ASCII Decoder

The module expects ASCII character code (in 8-bit binary) and displays the coresponding character on single digit 14-segment monocolor LED display.…

License : LGPL
Language : VHDL

Signed Unsigned Multiplier and Divider Test Circuits

Goal: Implement signed/unsigned 32/16 bit multiplier/divider using a finite state machine (and use it for a fun project) Background: I needed a…

License : LGPL
Language : VHDL

Xilinx Virtex FLoating Point Library

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License : LGPL
Language : VHDL

Superscalar Version Of DLX Processor

The DLX processor is an academic processor described in in John L. Hennessy and David A. Patterson's Computer Architecture: A Quantitative…

License : LGPL
Language : VHDL

Tanh Approximation Custom Instruction for NIOS II

A custom instruction for approximation of the hyperbolic tangent function tanh(x) with a max. error of 0.1

License : LGPL
Language : VHDL

YAC - Yet Another CORDIC for Hardware Effecient Calculation

CORDIC is the acronym for COordinate Rotation DIgital Computer and allows a hardware efficient calculation of various functions like - atan, sin,…

License : LGPL
Language : VHDL

128-bit Pseudo Random Number Generator Using LFSR

This PRNG uses Fibonacci LFSRs with a estimated period of 3.40282366920938463463374607431768211455 × 10^38 clock cycles Expression: X^128 + X^126…

License : LGPL
Language : VHDL