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Category: Communication Controller IP Cores (87)

Core1990 : Royalty-free Interlaken Protocol

Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…

License : LGPL
Language : VHDL

1Gbit Ethernet UDP IP Stack

Implements UDP, IPv4, ARP protocols Zero latency between UDP and MAC layer (combinatorial transfer during user data phase) Allows full control of…

License : BSD
Language : VHDL

Open-source FPGA Communication Framework

FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a…

License : BSD
Language : Verilog & VHDL

Ethernet 100/1000 Mbps

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

Minimal UART Core

This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…

License : LGPL
Language : VHDL

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL

UDP/IP Core

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : GPL
Language : VHDL

1G Ethernet ARP Communication Controller FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

VHDL Standard 16550 UART Core

A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses Features Uses parts from the…

Language : VHDL

A Generic VHDL 8b/10b Protocol Encoder and Decoder

This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b…

License : GPL
Language : VHDL

Ethernet Switch on Configurable Logic

n/a

License : LGPL
Language : VHDL

A VHDL CAN Protocol Controller

A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller To Download, click at the "Downloads" button upper…

Language : VHDL

ADAT Lightpipe Optical Datastream Receiver

This is a feed forward receiver for an ADAT lightpipe optical datastream. This type of multichannel audio connection is widely used in professional…

Language : VHDL

AMI and HDB1 Line Codes in VHDL Implementation

VHDL implementation of the AMI --- Alternate Mark Inversion --- and HDB1 --- High Density Bipolar of order 1 line codes. For other line code refer…

Language : VHDL

SATA AHCI Controller Drivers

please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi

License : LGPL
Language : Verilog & VHDL

DQPSK Symbol Mapper

DQPSK symbol mapper suitable for TETRA/APCO-25 physical layer.

License : GPL
Language : VHDL

Fade Light L3 Ethernet PHY Protocol

This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an…

License : Others
Language : VHDL

FPGA remote slow control via UART 16550

Control the activity and status of your FPGA by targeting a memory mapped space inside it. Based on: -- elements from the GH libraries…

License : LGPL
Language : VHDL

High-speed FT2232H USB Avalon Core

The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style…

License : Others
Language : VHDL

FT245R USB FIFO Interface

n/a

License : LGPL
Language : VHDL