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Category: Communication Controller IP Cores (5)

SATA Controller in Verilog

Sata stack written in Verilog , , Staus: , , , ,Nysa SATA Github, , , Code Organization: , , sata_stack.v (Top File that applications interface…

License : Others
Language : Verilog

Bidirectional TCP Socket for FPGA

TCP Socket TCP Socket is a TCP/IP stack implementation. The core acts as a server, allowing a remote client to establish a bidirectional TCP socket…

License : Others
Language : Verilog

vSPI - Verilog Implementation of SPI Slave

=== What's "vSPI"? === vSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably…

License : Others
Language : Verilog

ARINC 429 Transmitter And Receiver

The aim of this project is to provide a set of ARINC-429-compatible TX and RX synthesizable interfaces. The transmitting interface serializes a…

License : Others
Language : Verilog

Documented Verilog UART

Open Source Documented Verilog UART Purpose This module was created as a result of my own need for a UART (serial line I/O) component and…

License : Others
Language : Verilog