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Category: Communication Controller IP Cores (49)

IEEE 802.3-2008 Clause 36 PCS 1000BASE-X

Verilog implementation of IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS) type 1000BASE-X (1000baseLX and/or 1000baseSX)

License : LGPL
Language : Verilog

10/100M Ethernet-FIFO Convertor

Flow Summary Compiled in Quartus 9.0 +-------------------------------------------------------------------------------+ ; Flow Summary ;…

License : LGPL
Language : Verilog

10/100/1000 Mbps tri-mode Ethernet MAC Controller

mail group is added to track all the Q&A from the author. If you have any question about the design, please send your question to mail group.…

License : LGPL
Language : Verilog

100 Mbps Ethernet MAC Layer Switch

Ethernet MAC Layer Switch. The switch receive 100 MB/s data rate from 6 channels and direct each frame received to its destination port. The switch…

License : LGPL
Language : Verilog

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. Features 1. Interfaces - XGMII…

License : LGPL
Language : Verilog

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL

SPORT Interface

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

USB To UART

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

1G Ethernet DPI in Verilog

Current project provides idea of complex network design verification via [{Linux-tunnel interface} + SystemVerilog DPI-C}].

License : LGPL
Language : Verilog

Ethernet MAC 10/100 Mbps for CSMA/CD LAN

The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation…

License : LGPL
Language : Verilog

APB SPI Design Transmission

APB SPI design is meant to be interfaced with slow-speed peripherals. The initial design will contain APB slave on one side, which will initiate…

License : LGPL
Language : Verilog

SATA AHCI Controller Drivers

please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi

License : LGPL
Language : Verilog & VHDL

Asynchronous SPI Master in Verilog

This is a Verilog language asynchronous SPI, this mean that the controller can have a different clock frequency than SPI module. On the simulate…

License : LGPL
Language : Verilog

Verilog Bitwise Addressable GPIO

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

Cheap Ethernet Interface for FPGAs

Cheap Ethernet interface Realization of Ethernet interface and protocols optimized for minimal external components and FPGA resources. FPGA may…

License : LGPL
Language : Verilog

Ethernet 10GE Low Latency MAC

This is a fork of the xge_mac and was released by the Computer Architecture Group (http://cag.uni-hd.de) of the University of Heidelberg. Main…

License : LGPL
Language : Verilog

Hardware Assisted IEEE 1588 IP Core

Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE…

License : LGPL
Language : Verilog

I2C Slave to Wishbone Master Interface

I2C slave to WishBone master interface.

License : LGPL
Language : Verilog

I2C Repeater in SystemVerilog

This is a quick module I hacked together to connect two I2C buses to work around a hardware bug on a board. It mostly works, and I'm posting it…

License : LGPL
Language : Verilog

I2C GPIO Expander Board Using Verilog Code

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License : LGPL
Language : Verilog