Or try an example search: AES128
Introducing Calibre nmLVS-Recon
Implements UDP, IPv4, ARP protocols Zero latency between UDP and MAC layer (combinatorial transfer during user data phase) Allows full control of…
FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a…
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the…
The IICMB core provides low-speed, two-wire, bidirectional serial bus interfaces compliant to industry standard I2C protocol. The key feature of…
This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T…
This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine. This is a work in progress.…
This is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit. + baudX8/X16 mode selects in…
This is a scan based serial communication block designed to safely and easily move data onto and off of a chip with a minimal number of pins.…
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
Have you ever needed a fast and easy way to test your new FPGA board? You know you have all the interfaces but it will take time to finish the…
VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…
Wrimm provides Wishbone interconnect functionality, multi-master arbitration, multi-slave partial address deccoding and bus multiplexing. Wrimm…
Since lots of people ask me questions about my core, i want to clarify some things: 1) the master works, the slave is not entirely thought-through,…
Don't have an AAC account? Create one now.
Forgot your password? Click here.