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Category: Communication Controller IP Cores (13)

1Gbit Ethernet UDP IP Stack

Implements UDP, IPv4, ARP protocols Zero latency between UDP and MAC layer (combinatorial transfer during user data phase) Allows full control of…

License : BSD
Language : VHDL

Open-source FPGA Communication Framework

FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a…

License : BSD
Language : Verilog & VHDL

Wishbone I2C Controller Core for Communications

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the…

License : BSD
Wishbone Version : B.3
Language : Verilog

IICMB Core - I2C Multiple Bus Controller

The IICMB core provides low-speed, two-wire, bidirectional serial bus interfaces compliant to industry standard I2C protocol. The key feature of…

License : BSD
Language : VHDL

HDB3/HDB2/B3ZS Encoder Decoder

This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T…

License : BSD
Language : VHDL

ISO7816 3 Master on FPGA

This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine. This is a work in progress.…

License : BSD
Language : Verilog

RTF Simple UART Core with BAUD Generator

This is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit. + baudX8/X16 mode selects in…

License : BSD
Language : Verilog

Scan Based Serial Communication Block

This is a scan based serial communication block designed to safely and easily move data onto and off of a chip with a minimal number of pins.…

License : BSD
Language : Verilog

SDHC Self Configuring Core

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : BSD
Language : VHDL

UART to Bus IP Core for Fast and Easy Test FPGA

Have you ever needed a fast and easy way to test your new FPGA board? You know you have all the interfaces but it will take time to finish the…

License : BSD
Language : Verilog & VHDL

UDP/IP Core for PC-FPGA Communication

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : BSD
Language : Verilog

WRIMM Based Wishbone Interconnect System

Wrimm provides Wishbone interconnect functionality, multi-master arbitration, multi-slave partial address deccoding and bus multiplexing. Wrimm…

License : BSD
Language : VHDL

I2C Master Slave Core

Since lots of people ask me questions about my core, i want to clarify some things: 1) the master works, the slave is not entirely thought-through,…

License : BSD
Language : VHDL