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Category: Communication Controller IP Cores (68)

Core1990 : Royalty-free Interlaken Protocol

Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…

License : LGPL
Language : VHDL

Ethernet 100/1000 Mbps

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

Minimal UART Core

This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…

License : LGPL
Language : VHDL

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL

UDP/IP Core

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : GPL
Language : VHDL

1G Ethernet ARP Communication Controller FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

A Generic VHDL 8b/10b Protocol Encoder and Decoder

This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b…

License : GPL
Language : VHDL

Ethernet Switch on Configurable Logic

n/a

License : LGPL
Language : VHDL

SATA AHCI Controller Drivers

please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi

License : LGPL
Language : Verilog & VHDL

DQPSK Symbol Mapper

DQPSK symbol mapper suitable for TETRA/APCO-25 physical layer.

License : GPL
Language : VHDL

FPGA remote slow control via UART 16550

Control the activity and status of your FPGA by targeting a memory mapped space inside it. Based on: -- elements from the GH libraries…

License : LGPL
Language : VHDL

FT245R USB FIFO Interface

n/a

License : LGPL
Language : VHDL

Gamepads Controllers for FPGAs

This project contains a collection of cores that interface with various gamepads. Each gamepad type has a dedicated controller core which handles…

License : GPL
Language : VHDL

GPIB Core (IEEE-488) Controller

Project content: trunk/vhdl - source of this open core trunk/prototype_1 - example prototype using the GPIB core trunk/prototype_1/fpga - xilinx…

License : GPL
Language : VHDL

IEEE 802.15.4 Standard (TX,RX) Physical Layer in VHDL

VHDL implementation of the physical layer of the IEEE 802.15.4 standard (TX, RX). The doc/ directory of the repository contains the thesis related…

License : GPL
Language : VHDL

OP2P (Open Peer to Peer Interface) Wishbone Aurora Bridge

Open Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P). This interface logic has been designed to provide a very high performance multi-lane…

License : LGPL
Language : VHDL

I2S 3-Wire Interface for Audio Streaming

I2S is an industry standard (invented by Philips) 3-wire interface for streaming stereo audio between devices. Typical applications include digital…

License : GPL
Language : VHDL

LPC ROM Emulator on USB Dongle Core

Main features of latest v5 HW are: -LPC memory read (can be disabled),LPC Firmware Hub memory read and IO write for POST Code capture (and display…

License : LGPL
Language : VHDL

I2S to Paralell ADC/DAC Controller

I2S to Paralell ADC/DAC controller This provides a bridge between a paralell device (such as a microcontroller (uC) and an I2S (!not! I2C) audio…

License : GPL
Language : VHDL

I2S Serial Device to Parallel Interface

I2S to Parallel Interface This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device…

License : GPL
Language : VHDL