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Category: Communication Controller IP Cores (48)

Core1990 : Royalty-free Interlaken Protocol

Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…

License : LGPL
Language : VHDL

Ethernet 100/1000 Mbps

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

Minimal UART Core

This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…

License : LGPL
Language : VHDL

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL

1G Ethernet ARP Communication Controller FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

Ethernet Switch on Configurable Logic

n/a

License : LGPL
Language : VHDL

SATA AHCI Controller Drivers

please check the source code from: https://github.com/linuxbestahci https://github.com/linuxbestahci_mpi

License : LGPL
Language : Verilog & VHDL

FPGA remote slow control via UART 16550

Control the activity and status of your FPGA by targeting a memory mapped space inside it. Based on: -- elements from the GH libraries…

License : LGPL
Language : VHDL

FT245R USB FIFO Interface

n/a

License : LGPL
Language : VHDL

OP2P (Open Peer to Peer Interface) Wishbone Aurora Bridge

Open Peer to Peer Interface, Wishbone to Aurora Bridge (OP2P). This interface logic has been designed to provide a very high performance multi-lane…

License : LGPL
Language : VHDL

LPC ROM Emulator on USB Dongle Core

Main features of latest v5 HW are: -LPC memory read (can be disabled),LPC Firmware Hub memory read and IO write for POST Code capture (and display…

License : LGPL
Language : VHDL

JTAG Master in VHDL

This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag)

License : LGPL
Language : VHDL

JTAG Slave / BoundaryScan Slave in VHDL

project is closed at the moment.

License : LGPL
Language : VHDL

MADI Receiver (AES 10) with 8x ADAT Optical

This is a receiver for a Multichannel Audio Digital Interface (MADI), also known as AES-10. This type of fibreoptical or electrical connection is…

License : LGPL
Language : VHDL

Manchester Decoder for Wireless

This core decodes incoming Manchester encoded data. The core is easily modified for your particular project, in that there are just a few constants…

License : LGPL
Language : VHDL

The Manchester UART Communication Controller

This is a Manchester encoded UART that enables runing small periferals with parasitic power derived from the TXD line, and allowing large clock…

License : LGPL
Language : VHDL

Multi Microphone Interface System

Introduction The system is an Interface between the Analog Digital Converter (ADC) and a PC connected by Ethernet. And the system is based the…

License : LGPL
Language : VHDL

OPB SPI Clock Independent Core

The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the…

License : LGPL
Language : VHDL

Simple One Wire Controller with DS1820

A simple one-wire controller that does not require a CPU to operate. Also included is a higher level DS1820 controller that implements the search,…

License : LGPL
Language : VHDL

OPB_usblite Compatible with USB CDC

opb_usblite - opb_uartlite replacement for Xilinx Microblaze processor written in VHDL and Verilog. The opb_usblite is compatible with the USB CDC…

License : LGPL
Language : VHDL