Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: AES128

Filters

Category: Communication Controller IP Cores (11)

SpaceWire SystemC

If you liked our work is want to help contribute to the future progress of others who have seen help us by donating. ###…

License : Others
Language : Other

Fade Light L3 Ethernet PHY Protocol

This project implements the simple and light protocol for transmission of data from low resources FPGA connected to the Ethernet PHY and an…

License : Others
Language : VHDL

High-speed FT2232H USB Avalon Core

The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style…

License : Others
Language : VHDL

SATA Controller in Verilog

Sata stack written in Verilog , , Staus: , , , ,Nysa SATA Github, , , Code Organization: , , sata_stack.v (Top File that applications interface…

License : Others
Language : Verilog

Simple UART Contorller for FPGAs

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART…

License : Others
Language : VHDL

Bidirectional TCP Socket for FPGA

TCP Socket TCP Socket is a TCP/IP stack implementation. The core acts as a server, allowing a remote client to establish a bidirectional TCP socket…

License : Others
Language : Verilog

UART 8 SystemC Implementation

This is a simple UART implementation with intention to valid ASIC learning and use it on simple applications. The environment was rebuild with…

License : Others
Language : Other

vSPI - Verilog Implementation of SPI Slave

=== What's "vSPI"? === vSPI is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably…

License : Others
Language : Verilog

Universal Configurable Wishbone AXI with Xilinx IP Wrapper

WishboneAXI This project is a universal, configurable Wishbone AXI bridge together with Xilinx IP wrapper, which makes it suitable for Block Design…

License : Others
Wishbone Version : B.3
Language : VHDL

ARINC 429 Transmitter And Receiver

The aim of this project is to provide a set of ARINC-429-compatible TX and RX synthesizable interfaces. The transmitting interface serializes a…

License : Others
Language : Verilog

Documented Verilog UART

Open Source Documented Verilog UART Purpose This module was created as a result of my own need for a UART (serial line I/O) component and…

License : Others
Language : Verilog