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Category: Crypto Core IP Cores (38)

Flexible Design of a Modular Simultaneous Exponentiation Core

Project information The Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations in…

License : LGPL
Language : VHDL

AES Encoder and Decoder Modules

Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added…

Language : VHDL

AES 128 Advanced Encryption Standard Algorithm

This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…

License : LGPL
Language : VHDL

AES 128 Three Implementations in VHDL

Three different implementations of the AES-128 (VHDL).

License : GPL
Language : VHDL

128-bit AES Decryption Core

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

AES Encryption All Keylength

Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely,…

License : BSD
Language : VHDL

Avalon AES ECB Core (128, 192, 256 Bit)

General Description I know there are plenty of AES (Rijndael) implementations around. I created my own anyway because I was unhappy with either the…

License : BSD
Language : VHDL

B-163 EC Arithmetic

Bit-serial multiplication on the NIST B-163 curve. This implementation utilizes DSP481E blocks (Artix-7 FPGA).

License : GPL
Language : VHDL

Bitcoin Double SHA256 for FPGA/ASIC

The module is designed and optimized for Bitcoin hash work on FPGA or ASIC.

License : LGPL
Language : VHDL

Modular Montgomery Multiplier and Exponentiation

Modular multiplication and modular exponentiation play an important role in the most of existing cryptographic systems. In fact these are time and…

License : LGPL
Language : VHDL

Camellia Block Cipher Cores

Camellia block cipher cores. Features The project is composed of different cores: Performance optimized: exploits pipelining in order to maximize…

License : GPL
Language : VHDL

Compact Hardware CLEFIA Structure for FPGAs

The main goal on this research work was to provide a compact hardware CLEFIA structure, while still being able to achieve implementations with…

License : LGPL
Language : VHDL

Pipelined Crypto-PAn 128-bit AES

Crypto-PAn A hardware implementation of Crypto-PAn[1]. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the…

License : GPL
Language : VHDL

Classic DES Block Cipher Core

VHDL implementation of the classic DES block cipher (iterative architecture).

License : GPL
Language : VHDL

DESL Core VHDL Implementation

VHDL implementation of the DESL block cipher (iterative architecture).

License : GPL
Language : VHDL

DESLX Core Block Cipher in VHDL

VHDL implementation of the DESLX block cipher (iterative architecture).

License : GPL
Language : VHDL

DESX Block Cipher Core in VHDL Implementation

VHDL implementation of the DESX block cipher (iterative architecture).

License : GPL
Language : VHDL

IOTA PoW Computation Pearl-Driver for FPGAs

Overview IOTA PoW needs a lot of computational power which makes sending transactions on smaller microcontrollers (like ARM) very slow. This is a…

License : Others
Language : VHDL

Simple to Use SHA-2 Algorithm

Simple to use SHA-2 algorithm Is a VHDL implementation of SHA-224/256 core. Major project choice is semplicity: just feed core with message a chunk…

License : LGPL
Language : VHDL

Mini Advanced Encryption Standard - Mini AES

Mini AES Advanced Encryption Standard (AES) implementation with small area/resources utilization. Features - Encryption and Decryption unit in…

License : BSD
Language : VHDL