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Category: Crypto Core IP Cores (27)

Flexible Design of a Modular Simultaneous Exponentiation Core

Project information The Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations in…

License : LGPL
Language : VHDL

AES 128 Advanced Encryption Standard Algorithm

This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…

License : LGPL
Language : VHDL

AES 128 Three Implementations in VHDL

Three different implementations of the AES-128 (VHDL).

License : GPL
Language : VHDL

128-bit AES Decryption Core

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL

B-163 EC Arithmetic

Bit-serial multiplication on the NIST B-163 curve. This implementation utilizes DSP481E blocks (Artix-7 FPGA).

License : GPL
Language : VHDL

Bitcoin Double SHA256 for FPGA/ASIC

The module is designed and optimized for Bitcoin hash work on FPGA or ASIC.

License : LGPL
Language : VHDL

Modular Montgomery Multiplier and Exponentiation

Modular multiplication and modular exponentiation play an important role in the most of existing cryptographic systems. In fact these are time and…

License : LGPL
Language : VHDL

Camellia Block Cipher Cores

Camellia block cipher cores. Features The project is composed of different cores: Performance optimized: exploits pipelining in order to maximize…

License : GPL
Language : VHDL

Compact Hardware CLEFIA Structure for FPGAs

The main goal on this research work was to provide a compact hardware CLEFIA structure, while still being able to achieve implementations with…

License : LGPL
Language : VHDL

Pipelined Crypto-PAn 128-bit AES

Crypto-PAn A hardware implementation of Crypto-PAn[1]. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the…

License : GPL
Language : VHDL

Classic DES Block Cipher Core

VHDL implementation of the classic DES block cipher (iterative architecture).

License : GPL
Language : VHDL

DESL Core VHDL Implementation

VHDL implementation of the DESL block cipher (iterative architecture).

License : GPL
Language : VHDL

DESLX Core Block Cipher in VHDL

VHDL implementation of the DESLX block cipher (iterative architecture).

License : GPL
Language : VHDL

DESX Block Cipher Core in VHDL Implementation

VHDL implementation of the DESX block cipher (iterative architecture).

License : GPL
Language : VHDL

Simple to Use SHA-2 Algorithm

Simple to use SHA-2 algorithm Is a VHDL implementation of SHA-224/256 core. Major project choice is semplicity: just feed core with message a chunk…

License : LGPL
Language : VHDL

PRESENT - 32 bit Hardware Lightweight Block Cipher

Present is a lightweight block cipher dedicated to implement in Hardware. It was developed by Knudsen team. This cipher operates on the 64 bit text…

License : LGPL
Language : VHDL

NOEKEON Core (Lightweight Block Cipher)

VHDL implementation of the NOEKEON block cipher (iterative architecture).

License : GPL
Language : VHDL

GridVortex SHA256 Hash Core Algorithm

This is the GV_SHA256, a fast SHA-256 engine (580Mbps @ 74MHz), fully compliant to the NIST FIPS-180-4 SHA-256 approved algorithm. It is…

License : LGPL
Language : VHDL

Pipelined Architecture of AES 128 Bit

This is a fully pipelined implementation of the AES (rijndael) cipher with 128 bit keysize. Post place and route logs show the maximum speed to be…

License : LGPL
Language : VHDL

RC6 Cryptography Algorithm in VHDL

The Cryptographic Algorithm which is most widely used throughout the world for protecting information. Cryptography is the art of secret writing,…

License : GPL
Language : VHDL