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Category: Crypto Core IP Cores (11)

HIGHT Crypto Core

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License : LGPL
Language : Verilog

AES Decryption Core for FPGA Implementations

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…

License : LGPL
Language : Verilog

AES SystemVerilog Behavioral Model

The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…

License : LGPL
Language : Verilog

Pipelined AES 128 Encryption Module

The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…

License : LGPL
Language : Verilog

High Throughput Low Area AES Core

The High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone…

License : LGPL
Language : Verilog

MD5 Pipelined Implementations in Verilog

A high throughput, 64-stage pipelined implementation of MD5 written in Verilog. Completes one hash per cycle.

License : LGPL
Language : Verilog

Present - Block Cipher Encryption Core

About Present Block Cipher Present is a lightweight block cipher designed for hardware constrained applications such as RFID tags and Smart Cards.…

License : LGPL
Language : Verilog

RC4 Pseudo-random Stream Generator

RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then…

License : LGPL
Language : Verilog

Secure Hash Algorithm - SHA Cores in VerilogHDL

This is a collection of SHA(Secure Hash Algorithm) cores. These include SHA-1, SHA-2 algorithms. These cores are non-pipelined version of SHA, and…

License : LGPL
Language : Verilog

Bit-Serialized Simon Block Cipher Core

The code presented here implements the bit-serialized SIMON block cipher. Please check the following publication for the details of the…

License : LGPL
Language : Verilog

XTEA Block Xipher Crypto Core in Verilog

This is a Verilog implementation of the XTEA block cipher. It works on two 32-bit blocks of data at a time with a 128-bit key. A proper OpenCores…

License : LGPL
Language : Verilog