Search our IC Design Center for IP Cores and IC Design Related Content.

Or try an example search: AES128

Filters

Category: Crypto Core IP Cores (22)

Fast AES-128 Encryption Only Cores

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : Verilog

HIGHT Crypto Core

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

Floating Point Unit - An IEEE 754 Compliant

This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as…

Language : Verilog

Three Cores AES Encryption Algorithm

AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS…

License : Others
Language : Verilog

Simple AES (Rijndael) on Xilinx Spartan Series

Simple AES (Rijndael) IP Core. I have tried to balance this implementation and to trade off size and performance. The goal was to be able to fit in…

Language : Verilog

AES Encryption Algorithm 128/192 Bits

Here you can find two different implementations of AES encryption algorithm: - A 128 bits AES algorithm focusing on very low area applications. - A…

Language : Verilog

AES Decryption Core for FPGA Implementations

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…

License : LGPL
Language : Verilog

AES SystemVerilog Behavioral Model

The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…

License : LGPL
Language : Verilog

Pipelined AES 128 Encryption Module

The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…

License : LGPL
Language : Verilog

BTC Miner - An Open Source Bitcoin Miner

BTCMiner is a Bitcoin Miner software which allows you to make money with your ZTEX USB-FPGA Module. Since these FPGA Boards contain an USB…

License : GPL
Language : Verilog

Open-Source Simple DES/Triple DES Core

Simple DES/Triple-DES core. Motivation - A simple DES core - Fast and Small Version - Open Source Compatibility I believe that the core complies to…

Language : Verilog

AES with Galois Counter Mode in FPGA

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : Verilog

GOST 28147-89 Core Implementation on Xilinx

This is a implementation of the GOST 28147-89 - a Soviet and Russian government standard symmetric key block cipher. GOST 28147-89 has a 64-bit…

License : BSD
Language : Verilog

GOST 28147-89 Block Cipher

The GOST block cipher, defined in standard GOST 28147-89, is a Soviet and Russian government standard symmetric key block cipher. Developed in the…

License : BSD
Language : Verilog

High Throughput Low Area AES Core

The High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone…

License : LGPL
Language : Verilog

MD5 Pipelined Implementations in Verilog

A high throughput, 64-stage pipelined implementation of MD5 written in Verilog. Completes one hash per cycle.

License : LGPL
Language : Verilog

Present - Block Cipher Encryption Core

About Present Block Cipher Present is a lightweight block cipher designed for hardware constrained applications such as RFID tags and Smart Cards.…

License : LGPL
Language : Verilog

RC4 Pseudo-random Stream Generator

RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then…

License : LGPL
Language : Verilog

NIST SHA-3 Algorithm (Keccak)

SHA-3, originally known as Keccak [1], is a cryptographic hash function selected as the winner of the NIST hash function competition [2]. Because…

License : Others
Language : Verilog

Secure Hash Algorithm - SHA Cores in VerilogHDL

This is a collection of SHA(Secure Hash Algorithm) cores. These include SHA-1, SHA-2 algorithms. These cores are non-pipelined version of SHA, and…

License : LGPL
Language : Verilog