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Introducing Calibre nmLVS-Recon
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While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…
The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…
The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…
The High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone…
A high throughput, 64-stage pipelined implementation of MD5 written in Verilog. Completes one hash per cycle.
About Present Block Cipher Present is a lightweight block cipher designed for hardware constrained applications such as RFID tags and Smart Cards.…
RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then…
This is a collection of SHA(Secure Hash Algorithm) cores. These include SHA-1, SHA-2 algorithms. These cores are non-pipelined version of SHA, and…
The code presented here implements the bit-serialized SIMON block cipher. Please check the following publication for the details of the…
This is a Verilog implementation of the XTEA block cipher. It works on two 32-bit blocks of data at a time with a 128-bit key. A proper OpenCores…
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