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Category: Crypto Core IP Cores (40)

HIGHT Crypto Core

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License : LGPL
Language : Verilog

Flexible Design of a Modular Simultaneous Exponentiation Core

Project information The Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations in…

License : LGPL
Language : VHDL

AES 128 Advanced Encryption Standard Algorithm

This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…

License : LGPL
Language : VHDL

AES Decryption Core for FPGA Implementations

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…

License : LGPL
Language : Verilog

AES 128 Three Implementations in VHDL

Three different implementations of the AES-128 (VHDL).

License : GPL
Language : VHDL

AES SystemVerilog Behavioral Model

The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…

License : LGPL
Language : Verilog

128-bit AES Decryption Core

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License : LGPL
Language : VHDL

Pipelined AES 128 Encryption Module

The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…

License : LGPL
Language : Verilog

B-163 EC Arithmetic

Bit-serial multiplication on the NIST B-163 curve. This implementation utilizes DSP481E blocks (Artix-7 FPGA).

License : GPL
Language : VHDL

Bitcoin Double SHA256 for FPGA/ASIC

The module is designed and optimized for Bitcoin hash work on FPGA or ASIC.

License : LGPL
Language : VHDL

Modular Montgomery Multiplier and Exponentiation

Modular multiplication and modular exponentiation play an important role in the most of existing cryptographic systems. In fact these are time and…

License : LGPL
Language : VHDL

BTC Miner - An Open Source Bitcoin Miner

BTCMiner is a Bitcoin Miner software which allows you to make money with your ZTEX USB-FPGA Module. Since these FPGA Boards contain an USB…

License : GPL
Language : Verilog

Camellia Block Cipher Cores

Camellia block cipher cores. Features The project is composed of different cores: Performance optimized: exploits pipelining in order to maximize…

License : GPL
Language : VHDL

Compact Hardware CLEFIA Structure for FPGAs

The main goal on this research work was to provide a compact hardware CLEFIA structure, while still being able to achieve implementations with…

License : LGPL
Language : VHDL

Pipelined Crypto-PAn 128-bit AES

Crypto-PAn A hardware implementation of Crypto-PAn[1]. The core makes use of a fully pipelined 128-bit AES (Rijndael) cipher engine as the…

License : GPL
Language : VHDL

Classic DES Block Cipher Core

VHDL implementation of the classic DES block cipher (iterative architecture).

License : GPL
Language : VHDL

DESL Core VHDL Implementation

VHDL implementation of the DESL block cipher (iterative architecture).

License : GPL
Language : VHDL

DESLX Core Block Cipher in VHDL

VHDL implementation of the DESLX block cipher (iterative architecture).

License : GPL
Language : VHDL

DESX Block Cipher Core in VHDL Implementation

VHDL implementation of the DESX block cipher (iterative architecture).

License : GPL
Language : VHDL

High Throughput Low Area AES Core

The High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone…

License : LGPL
Language : Verilog