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Category: Crypto Core IP Cores (25)

HIGHT Crypto Core

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License : LGPL
Language : Verilog

Flexible Design of a Modular Simultaneous Exponentiation Core

Project information The Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations in…

License : LGPL
Language : VHDL

AES 128 Advanced Encryption Standard Algorithm

This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…

License : LGPL
Language : VHDL

AES Decryption Core for FPGA Implementations

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…

License : LGPL
Language : Verilog

AES SystemVerilog Behavioral Model

The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…

License : LGPL
Language : Verilog

128-bit AES Decryption Core

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License : LGPL
Language : VHDL

Pipelined AES 128 Encryption Module

The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…

License : LGPL
Language : Verilog

Bitcoin Double SHA256 for FPGA/ASIC

The module is designed and optimized for Bitcoin hash work on FPGA or ASIC.

License : LGPL
Language : VHDL

Modular Montgomery Multiplier and Exponentiation

Modular multiplication and modular exponentiation play an important role in the most of existing cryptographic systems. In fact these are time and…

License : LGPL
Language : VHDL

Compact Hardware CLEFIA Structure for FPGAs

The main goal on this research work was to provide a compact hardware CLEFIA structure, while still being able to achieve implementations with…

License : LGPL
Language : VHDL

High Throughput Low Area AES Core

The High Throughput Low Area AES IP core implements the Rijndael encryption & decryption algorithm used in the AES standard. The standalone…

License : LGPL
Language : Verilog

Simple to Use SHA-2 Algorithm

Simple to use SHA-2 algorithm Is a VHDL implementation of SHA-224/256 core. Major project choice is semplicity: just feed core with message a chunk…

License : LGPL
Language : VHDL

MD5 Pipelined Implementations in Verilog

A high throughput, 64-stage pipelined implementation of MD5 written in Verilog. Completes one hash per cycle.

License : LGPL
Language : Verilog

PRESENT - 32 bit Hardware Lightweight Block Cipher

Present is a lightweight block cipher dedicated to implement in Hardware. It was developed by Knudsen team. This cipher operates on the 64 bit text…

License : LGPL
Language : VHDL

GridVortex SHA256 Hash Core Algorithm

This is the GV_SHA256, a fast SHA-256 engine (580Mbps @ 74MHz), fully compliant to the NIST FIPS-180-4 SHA-256 approved algorithm. It is…

License : LGPL
Language : VHDL

Pipelined Architecture of AES 128 Bit

This is a fully pipelined implementation of the AES (rijndael) cipher with 128 bit keysize. Post place and route logs show the maximum speed to be…

License : LGPL
Language : VHDL

Present - Block Cipher Encryption Core

About Present Block Cipher Present is a lightweight block cipher designed for hardware constrained applications such as RFID tags and Smart Cards.…

License : LGPL
Language : Verilog

RC4 Pseudo-random Stream Generator

RC4 PRBS (Generates the RC4 stream, then you have to XOR it with your data to crypt or decrypt it), takes 768 clocks to do key-expansion, then…

License : LGPL
Language : Verilog

512 Bit Open-Source RSA Algorithm

The project presents an open-source implementaion of the 512 bit RSA algorithm. This is a reduced version of a full FIPS Certified capable RSA…

License : LGPL
Language : VHDL

Salsa20 Stream Cipher 32-bit Based Pseudorandom Function

Salsa20 stream cipher is built on a pseudorandom function based on 32-bit addition, bitwise addition (XOR) and rotation operations, which maps a…

License : LGPL
Language : VHDL