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Category: DSP Core IP Cores (15)

LinkRunCCA : Linked List & Run-length-based Techniques

LinkRunCCA is a real-time single-pass connected component analysis/ connected component labeling (CCA/CCL) implemented in Verilog HDL. It can be…

License : LGPL
Language : Verilog

Fixed-Point Cascaded FIR Filter

FIR filter - architecture written with pure verilog - parameterizable in verilog code - cascaded - processing is paralleled - data and coefficients…

License : LGPL
Language : Verilog

Hogenauer Pruning CIC Filter

CIC filter It is the CIC filter with Hogenauer pruning. This project is based on https://opencores.org/projects/cic_core project. Differences are…

License : LGPL
Language : Verilog

Configurable High Speed Viterbi Decoder in Verilog

n/a

License : GPL
Language : Verilog

Double Clocked FFT Core

The goal of this project is to create an IP core for an FFT that runs, in a pipelined fashion, at two samples per clock. A C++ program will…

License : GPL
Language : Verilog

Dynamic Resizable Streaming FFT2

Integer streaming FFT fixed size and resizable. Language - SystemVerilog. Generator of rotation coefficients in MatLab. Includes Quartus project…

License : LGPL
Language : Verilog

8-bit Fast Hadamhard Transform for Xilinx FPGA

The RTL computes Fast Hadamhard Transform of 8-bit input data. The code has been developed using standard FHT algorithm using matrix addition. The…

Language : Verilog

Generic FIR Filter in RobustVerilog Parser

Generic FIR filter. Builds optimized filter according to number of multipliers, supports serial or parallel architecture. Supports delays in input.…

License : LGPL
Language : Verilog

IMA ADPCM Audio Compressor

The IMA ADPCM audio compression algorithm belongs to the Adaptive Differential Pulse Code Modulation type algorithms. The algorithm is based on a…

License : BSD
Language : Verilog

Low-pass Filter on FIR Linear-phase Structure

Low-pass filter using an FIR Linear-phase structure for more information please view README file.

License : LGPL
Language : Verilog

Digital PID Controller - Digital Proportional Integral Derivative Controller Algorithm

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first…

License : LGPL
Language : Verilog

Pipelined FFT/IFFT 128 Points Processor

Pipelined FFT/IFFT 128 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 128 – complex point…

License : LGPL
Language : Verilog

Pipelined FFT/IFFT 256 Points Processor

Pipelined FFT/IFFT 256 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 256 – complex point…

License : LGPL
Language : Verilog

Pipelined FFT/IFFT 64 Points Processor

Pipelined FFT/IFFT 64 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 – complex point…

License : LGPL
Language : Verilog

Pipelined Fixed Point Elementary Functions with CORDIC

Conveyored (result on every clock) elementary functions, implemented with CORDIC for demoscene project (http://www.youtube.comwatch?v=oh1_MzuFtdU).…

License : LGPL
Language : Verilog