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Category: ECC Core IP Cores (8)

Reed Solomon Encoder/Decoder

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License : LGPL
Language : Verilog

Configurable BCH Encoder and Decoder for FPGA

The project describes an IPCore in verilog about binary BCH encoder and decoder. BCH is a popular error correcting code used in storage and…

License : LGPL
Language : Verilog

Double Error Correcting (DEC) BCH Encoder / Decoder

The double error correcting (DEC) BCH encoder / decoder IP cores. Features : – allows to correct up to 2 errors. – supports…

License : LGPL
Language : Verilog

8-bit Wide Reed Solomon Decoder Encoder

This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and…

License : LGPL
Language : VHDL

Spread Spectrum modulator and demodulator using BPSK

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License : LGPL
Language : VHDL

DVB-RCS Turbo Decoder on SOVA Algorithm

This project features a double binary, DVB-RCS turbo decoder using the SOVA algorithm. Two models are included: - a MyHDL model, along with a…

License : LGPL
Language : VHDL

Yet Another Hamming Encoder and Decoder

A hamming encoder and decoder with single-error correcting and double-error detecting capability. The message length can be configured through a…

License : LGPL
Language : VHDL

Reed-Solomon Codec Generator

This tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec. - Selectable Decoder/Encoder/Both - Symbol width…

License : LGPL
Language : Verilog