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Category: ECC Core IP Cores (4)

Reed Solomon Encoder/Decoder

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

Configurable BCH Encoder and Decoder for FPGA

The project describes an IPCore in verilog about binary BCH encoder and decoder. BCH is a popular error correcting code used in storage and…

License : LGPL
Language : Verilog

Double Error Correcting (DEC) BCH Encoder / Decoder

The double error correcting (DEC) BCH encoder / decoder IP cores. Features : – allows to correct up to 2 errors. – supports…

License : LGPL
Language : Verilog

Reed-Solomon Codec Generator

This tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec. - Selectable Decoder/Encoder/Both - Symbol width…

License : LGPL
Language : Verilog