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Category: Memory Core IP Cores (16)

BRSFmnCE FPGA Implementation

This module implements a synchronous FIFO using Block RAM resources such as those found in SRAM-based FPGAs. This module has been used in several…

License : LGPL
Language : Verilog

32-bit CFI Flash Controller IP

CFI flash controller IP. Provides two modes of operation - simple (Wishbone bus straight through to flash bus, essentially, but with 32-bit word…

License : LGPL
Language : Verilog

Implementation of DDR3 SDRAM Controller for FPGAs (Controller Core)

This is a controller core for DDR3 SDRAM. Default configuration supports one 64 bit UDIMM or SO-DIMM Supports DIMM sizes of 1GB, 2GB, 4GB and 8GB…

License : LGPL
Language : Verilog

DDR2 mem controller for Digilent Genesys Board

n/a

License : LGPL
Language : Verilog

Configurable Direct Mapped Cache Controller

This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable…

License : LGPL
Language : Verilog

DPSFmnCE FIFO for UARTs

This project provides a parameterizable synchronous FIFO which uses LUTs instead of Block RAMs for its memory. The FIFO can be parameterized in…

License : LGPL
Language : Verilog

Wishbone Wrapper for Xilinx Memory Interface Generator (MIG)

Two WISHBONE wrappers will be developed for Xilinx Memory Interface Generator (MIG). The first is compliant with version B4 Registered Feedback…

License : LGPL
Language : Verilog

openHMC Controller - Configurable Open-Source Hybrid Memory Cube

openHMC is an open-source project developed by the Computer Architecture Group (CAG) at the University of Heidelberg in Germany. It is a…

License : LGPL
Language : Verilog

Open FreeList Module

Open FreeList Readme General Description The Open FreeList module is used to manage a set of variable sized packets inside a fixed memory block.…

License : LGPL
Language : Verilog

Versatile Memory Controller

Overview This is a modular memory controller supporting different types of memories. Initial design will have support for SDR SDRAM. Upcoming…

License : LGPL
Language : Verilog

Versatile FIFO Designs Using Verilog

The FIFO implementation outlined in this document can easily be configured to suit the following asynchronous FIFO with different clock domains for…

License : LGPL
Language : Verilog

Wishbone Asynchronous Memory Bridge

This project provides a bridge between asynchronous external memory interfaces found on many processors and a WishBone bus. It is being used on the…

License : LGPL
Language : Verilog

RAM_wb

This is a wishbone B3 compliant RAM memory. The memory array is defined as a 32 bit memory. This gives two valuable benefits. First. memory array…

License : LGPL
Language : Verilog

Synchronous_reset_fifo With Testbench

Description coming soon.

License : LGPL
Language : Verilog

Wishbone FLASH Interface For Parallel FLASH

Wishbone to Parallel FLASH interface with integral wait-state generator. This design has been used with the Intel StrataFlash Xilinx Spartan 3E…

License : LGPL
Language : Verilog

DDR3 Synthesizable BFM

This is a fully synthesizable DDR3 Memory BFM. Implemented using Verilog 2001 without any vendor specific IP Block. As such, the BFM is not able to…

License : LGPL
Language : Verilog