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Category: Memory Core IP Cores (12)

DDR2-SDRAM Controller on Xilinx Spartan-3A

This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board Function After a Power on : ================== 1. Init-Sequenz for the…

License : LGPL
Language : VHDL

2Q Cache Strategy on VHDL

Overview I implemented 2Q cache strategy from paper "2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm" written…

License : LGPL
Language : VHDL

FAT32 File System Parser

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License : LGPL
Language : VHDL

Functional RAM Simulation Models

The simu_mem project provides functional simulation models of commercially available RAMs. Advantages of the simu_mem models…

License : LGPL
Language : VHDL

Generic FIFO in VHDL

A very generic implementation of a FIFO. Makes good use of VHDL transactors for data transfers. Does not support Wishbone yet, but it's planned.

License : LGPL
Language : VHDL

NAND Controller (ONFI compliant)

n/a

License : LGPL
Language : VHDL

Parametrized FIFO based on SRL16E

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License : LGPL
Language : VHDL

Scratch DDR SDRAM Controller VHDL

DDR SDRAM controller core targeted at the mt46v32m16 chip on the Spartan3e Starter Board. The testbench synthesizes and runs on the targeted…

License : LGPL
Language : VHDL

Single Port ASRAM in VDHL

The main purpose of this project was two-fold. The first purpose was to implement a client-server test architecture based on Bergeron's work in…

License : LGPL
Language : VHDL

Verilog Single Port RAM to 3 Port RAM Wishbone Wrapper

This is a wrapper for an inferred single port RAM, that converts it into a Three-port RAM with one WISHBONE slave interface for each port. Very…

License : LGPL
Language : VHDL

SRL Feature FIFO in Xilinx FPGAs

Synchronous FIFO's based upon the SRL feature found in Xilinx FPGA's. Built to be small. In a Spartan 3, the 8 bit wide , 16 bit deep FIFO…

License : LGPL
Language : VHDL

Wishbone Interface for SPI FLASH

This module uses an interface to SPI serial FLASH memory devices to allow reading/writing/erasing of the FLASH. It includes a state machine that…

License : LGPL
Language : VHDL