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Category: Processor IP Cores (11)

ao486 - x86 Compatible Verilog Core

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX. The core was modeled and tested based on the Bochs software x86…

License : BSD
Language : Verilog

aoR3000 - MIPS R3000A Compatible Core

The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74…

License : BSD
Language : Verilog

Classic 5-Stage Pipeline MIPS 32-bit Processor

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a 1024 depth branch prediction buffer, a 2KB direct-mapped…

License : BSD
Language : Verilog

openMSP430 - Synthesizable 16-bit Microcontroller Core

Introduction The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430…

License : BSD
Language : Verilog

Software Aided Wishbone Extension For Xilinx (R) PicoBlaze (TM)

This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or…

License : BSD
Language : Verilog & VHDL

v586 - Soft Processor Core Compatible with 586 Instruction Set

This project is a soft processor core compatible with 586 instruction set. The processor core has AXI4 interface and uses XILINX AXI4 IPs such as…

License : BSD
Language : Verilog

MMU for Enhancement of Z80 and eZ80 Compatible Core or Physical Processor

mmu180 is a MMU (memory mananagement unit) designed per original specifications of Zilog's Z180 family of processors (including Hitachi…

License : BSD
Language : Verilog

TV80 8-bit Z80-Compatible Microprocessor Core

The TV80 is an 8-bit Z80-compatible microprocessor core, written in Verilog. It is based on Daniel Wallner's VHDL T80 core. Features - executes…

License : BSD
Language : Verilog

Y80e - Z80/Z180 Compatible Processor Softcore

Z80/Z180 compatible processor softcore. Based on Y80 project described in the book 'Microprocessor Design Using Verilog HDL' of Monte…

License : BSD
Language : Verilog

Infocom Z-Machine V3 | Z3 - The Zork CPU

A Verilog implementation of the Infocom Z-Machine V3. The spec the Z3 follows is http://inform-fiction.org/zmachine/standards/z1point0index.html.…

License : BSD
Language : Verilog

Ao68000 - Wishbone 68000 Core

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor. Introduction July 2011: Project copied to…

License : BSD
Language : Verilog