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Category: Processor IP Cores (60)

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

Introduction The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform…

License : LGPL
Language : Verilog

AltOr32 - Alternative Lightweight OpenRisc CPU

AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc…

License : LGPL
Language : Verilog

16-bit Classical CPU Based Loosely on Caxton Foster’s Blue CPU

A 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book "Computer Architecture". Includes a cross assembler…

License : LGPL
Language : Verilog

Simple RISC 32-bit Pipelined Processor

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

MC6809/HD6309 Compatible Core Processor

A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core. Goals: - Execute all implemented opcodes - Allow…

License : LGPL
Language : Verilog

A-Z80 CPU - Implementation of the Venerable Zilog Z80 Processor

Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices! A-Z80 is a conceptual implementation of the venerable…

License : LGPL
Language : Verilog

i650 - Verilog RTL Implementation of the Venerable IBM 650 Computer

A Verilog RTL implementation of the venerable IBM 650 computer. The goal of this project is to use available source materials to recreate a 650 as…

License : LGPL
Language : Verilog

MIPS32 Release 1 - 32-bit MIPS Bare-metal CPU Processor

UPDATE 1-Jan-2014: This project has moved to GitHub. Please visit https://github.com/granteamips32r1 for the latest code. No further changes will…

License : LGPL
Language : Verilog

AE18 - Clean Room Implementation of Microchip PIC18 Series

The AE18 is a clean room implementation of the Microchip PIC18 series CPU core using information from the PIC18C documentation from their website.…

License : LGPL
Language : Verilog

aeMB - EDK3.2 Clean Room Implementation Microblaze Core Compatible

The aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction…

License : LGPL
Language : Verilog

ag_6502 Soft Core with Phase-level Accuracy

The main features of ag_6502 implementation: * It provides not only clock-level compatibility, but phase-level compatibility too. Thus it may be…

License : GPL
Language : Verilog

Enhanced MIPS based on MIPS789 Opencores Project

This project is based on MIPS789 opencores project.We used MIPS789 core and added the cache infrastracture and AMBA bus from LEON3.The final core…

License : LGPL
Language : Verilog & VHDL

Amber ARM-compatible 32-bit RISC Core Processor

The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM® v2a instruction set…

License : LGPL
Language : Verilog

An Inventory Of Soft Processor Cores

Other project properties Category:Processor Language:Verilog & VHDL Development status:Alpha Additional info: WishBone compliant: No WishBone…

License : LGPL
Language : Verilog & VHDL

Attiny Atmega Xmega Configurable Atmel Core Processor

This is a configurable Atmel processor and support eight configurations: 1) REDUCED 2) MINIMAL 3) CLASSIC_8K 4) CLASSIC_128K 5) ENHANCED_8K 6)…

License : LGPL
Language : Verilog

Brainfuck CPU - Hardware Implementation

Brainfuck CPU is a hardware implementation of Brainfuck programing language. It uses simple 2-stage pipelining and Harvard's architecture. This…

License : LGPL
Language : Verilog

ECPU Arithmetic Logic Unit (ALU) in Verilog

Comments # ECPU 0.1.alpha # ============== # # Background # ======== # Resurrected university project originally written in VHDL. # Converted to…

License : GPL
Language : Verilog

Edge Processor Microarchitecture Implementation for MIPS1 ISA

Edge is a microarchitecture implementation for mips1 ISA. It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz…

License : LGPL
Language : Verilog

Educational 16-bit MIPS Processor

This project was aimed at providing people a simple, runnable, and easy-to-enhance MIPS CPU main architecture, along with well commented Verilog…

License : LGPL
Language : Verilog

R2000 Soc

n/a

License : LGPL
Language : Verilog