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Introducing Calibre nmLVS-Recon
microsemi用のAHBmaster.vhd…
Overview This package involves a PCIe Scatter-Gather DMA engine for Virtex5 and Virtex6. The design implements MAC, Physical (Xilinx Hard and Soft…
The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple…
pcie_mini IP core PCI-express to Wishbone Bridge for Xilinx FPGAs. Developer: Istvan Nagy, Bluechip Technology, 2011 Very often we want to make a…
The PCIe_DS_DMA core provides PCI Express controller for Xilinx HARD core for Virtex5, Virtex6, Spartan6, Artix 7 FPGA. Main features PCI Express…
This is a very simple PCI-target to Wishbone-master bridge. PCI-Target only, the bandwidth is quite low, fixed memory-image size (16MB), but it has…
rs232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user…
“pic” is a soft core, programmable interrupt controller which can be used as an interface between peripheral interrupt lines and…
Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory…
This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the…
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