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Category: System Controller IP Cores (12)

AHBmaster For FPGA Of Microsemi

microsemi用のAHBmaster.vhd…

License : LGPL
Language : VHDL

PCIe Scatter-Gather DMA Engine controller for Virtex5 and Virtex6

Overview This package involves a PCIe Scatter-Gather DMA engine for Virtex5 and Virtex6. The design implements MAC, Physical (Xilinx Hard and Soft…

License : LGPL
Language : VHDL

Configurable 32 Bit PCI Target

The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple…

License : LGPL
Language : VHDL

External Parallel to Internal Wishbone Master Interface Microcontroller

This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller. The external…

License : GPL
Language : VHDL

PCI-Express Mini to Wishbone Bridge for Xilinx FPGAs

pcie_mini IP core PCI-express to Wishbone Bridge for Xilinx FPGAs. Developer: Istvan Nagy, Bluechip Technology, 2011 Very often we want to make a…

License : LGPL
Language : VHDL

64 bit DMA Channel PCI Express controller

The PCIe_DS_DMA core provides PCI Express controller for Xilinx HARD core for Virtex5, Virtex6, Spartan6, Artix 7 FPGA. Main features PCI Express…

License : LGPL
Language : Verilog & VHDL

Wishbone Master Interface PCI Mini with 16 MB Memory Image

This is a very simple PCI-target to Wishbone-master bridge. PCI-Target only, the bandwidth is quite low, fixed memory-image size (16MB), but it has…

License : LGPL
Language : Verilog & VHDL

Synthesizeable Soft Core RS232 System Controller

rs232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user…

License : LGPL
Language : Verilog & VHDL

Programmable Interrupt Controller (PIC)

“pic” is a soft core, programmable interrupt controller which can be used as an interface between peripheral interrupt lines and…

License : LGPL
Language : VHDL

Wupper: PCIe DMA Engine for Xilinx Virtex-7 FPGA Gen3 Integrated Block

Wupper is designed by Nikhef (Amsterdam, The Netherlands) for the CERN ATLAS / FELIX project. Its main purpose is to provide a simple Direct Memory…

License : LGPL
Wishbone Version : B.4
Language : VHDL

WB LCD character display controller with Wishbone Interfaces

Overview LCD character display controller with Wishbone and memory mapped interfaces. It is compatible with the following parts: Sitronix ST7066U,…

License : LGPL
Language : Verilog

PCI Slave To WB Master

This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the…

License : LGPL
Language : VHDL